From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423413AbcB0BwK (ORCPT ); Fri, 26 Feb 2016 20:52:10 -0500 Received: from mezzanine.sirena.org.uk ([106.187.55.193]:40482 "EHLO mezzanine.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755218AbcB0BwJ (ORCPT ); Fri, 26 Feb 2016 20:52:09 -0500 Date: Sat, 27 Feb 2016 10:51:43 +0900 From: Mark Brown To: Pierre-Louis Bossart Cc: Mark Rutland , Oder Chiou , alsa-devel@alsa-project.org, Heiko Stuebner , Pawel Moll , Ian Campbell , linux-kernel@vger.kernel.org, Liam Girdwood , Takashi Iwai , Sugar Zhang , devicetree@vger.kernel.org, Rob Herring , Kumar Gala , Bard Liao Message-ID: <20160227015143.GV18327@sirena.org.uk> References: <1456190782-18865-1-git-send-email-sugar.zhang@rock-chips.com> <56CC719C.1090901@linux.intel.com> <2199435.lA9iTvxnKV@phil> <20160224033259.GL18327@sirena.org.uk> <56CDD5DD.6040006@linux.intel.com> <20160226010818.GZ18327@sirena.org.uk> <56D07293.902@linux.intel.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="fyFqtIrDrUc8SGBF" Content-Disposition: inline In-Reply-To: <56D07293.902@linux.intel.com> X-Cookie: Adapt. Enjoy. Survive. User-Agent: Mutt/1.5.24 (2015-08-30) X-SA-Exim-Connect-IP: 122.212.32.58 X-SA-Exim-Mail-From: broonie@sirena.org.uk Subject: Re: [alsa-devel] [PATCH] ASoC: rt5640: add master clock handling for rt5640 X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --fyFqtIrDrUc8SGBF Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Feb 26, 2016 at 09:43:15AM -0600, Pierre-Louis Bossart wrote: > Yes there are documentation and helpers I looked into, but to the best of my > limited knowledge not for the gate + dual-rate case. Then you jump to > complicated configurations combining multiple base clocks that don't really > make sense here. After one frustrating day of trying to wrap 100 lines of > code into the clock framework I gave up and kept the simple custom driver. > There is a single client for this clock so I don't quite see the > benefits/ROI of mapping a simple piece of hardware with a complex model. If the helpers aren't fitting your needs then surely just writing a simple driver with set rate and enable callbacks isn't going to be too hard? The wm831x driver was pretty trivial to write and seems to be on a similar order of complexity to this. --fyFqtIrDrUc8SGBF Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAEBCAAGBQJW0QEsAAoJECTWi3JdVIfQRQUH+wWufcVgRXjkOgaFnVY07VAC Cy1icjgUb+Soj9uNg8ndpozN80mkqnPAsbH5IjjEU4gVu5kxyG0wwd9ei3NjP/YE GsoFtEITrZc04Rg3GSJzpMCtV4v4unEt5KCyb6kH0Qoxlk+OamyUWNYnguyTv0fT x6VjRZydGSE8blzY8BjODnqpC78254Yad8aPLJiw2CvafTU5tzvhDNxYS0TPdijX X8wm68UG/q7QjI/uhR5UYH7O2PZyp2cY/RPt2A7ZPzy///1vSo5JRfj3JP/rHFSw LXSevfaUAbne5PFXJ+v3t8WokmNTNf4+DfUkoSnPGUEO+8aqMQFjbrIpVKBVt6s= =HNHK -----END PGP SIGNATURE----- --fyFqtIrDrUc8SGBF--