From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932625AbcCHJqj (ORCPT ); Tue, 8 Mar 2016 04:46:39 -0500 Received: from down.free-electrons.com ([37.187.137.238]:38027 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932084AbcCHJqc convert rfc822-to-8bit (ORCPT ); Tue, 8 Mar 2016 04:46:32 -0500 Date: Tue, 8 Mar 2016 10:46:28 +0100 From: Boris Brezillon To: Jiancheng Xue Cc: Brian Norris , , , , , , , , , , , , , , , , , , , , , , , , , , , , Binquan Peng Subject: Re: [RESEND PATCH v7] mtd: spi-nor: add hisilicon spi-nor flash controller driver Message-ID: <20160308104628.6224bde2@bbrezillon> In-Reply-To: <56DE9A79.30704@huawei.com> References: <1456474316-24473-1-git-send-email-xuejiancheng@huawei.com> <20160307225229.GC55664@google.com> <56DE9A79.30704@huawei.com> X-Mailer: Claws Mail 3.11.1 (GTK+ 2.24.27; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 8 Mar 2016 17:25:13 +0800 Jiancheng Xue wrote: > Hi Brian， > Thank you very much for your comments. > > On 2016/3/8 6:52, Brian Norris wrote: > [...] > >> > >> diff --git a/Documentation/devicetree/bindings/spi/spi-hisi-sfc.txt b/Documentation/devicetree/bindings/spi/spi-hisi-sfc.txt > >> new file mode 100644 > >> index 0000000..7407147 > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/spi/spi-hisi-sfc.txt > > > > This is not a SPI controller (or is it? it looks like a SPI NOR > > controller that doesn't do generic SPI), so it shouldn't go in the spi/ > > directory. > > > OK. I'll move this file into Documentation/devicetree/bindings/mtd. > > >> @@ -0,0 +1,25 @@ > >> +HiSilicon SPI-NOR Flash Controller > >> + > >> +Required properties: > >> +- compatible : Should be "hisilicon,hisi-sfc" and one of the following strings: > >> + "hisilicon,hi3519-sfc" > >> +- address-cells : number of cells required to define a chip select > >> + address on the SPI bus. Should be set to 1. See spi-bus.txt. > > > > This is not exactly a typical SPI bus, though I suppose some of that > > documentation could apply... > > > > OK. I'll modify the description. > > [...] > >> +static int hisi_spi_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, > >> + int len) > >> +{ > >> + struct hifmc_priv *priv = nor->priv; > >> + struct hifmc_host *host = priv->host; > >> + int ret; > >> + > >> + ret = hisi_spi_nor_send_cmd(nor, opcode, len); > >> + if (ret) > >> + return ret; > >> + > >> + memcpy(buf, host->iobase, len); > > > > sparse doesn't like any of these memcpy()'s, since that's __iomem. Are > > you sure you want a regular memcpy here, and elsewhere? > > > It's not a must to use memcpy though host->iobase represents a segment of inner memory > which stores data from flash device byte by byte. I will give up using memcpy here and > hisi_spi_nor_write_reg() in next version. Thank you! Or you can use memcpy_fromio(), which should give you better perfs than using readX() accessors in a loop. -- Boris Brezillon, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com