From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757622AbcDEIsb (ORCPT ); Tue, 5 Apr 2016 04:48:31 -0400 Received: from mga11.intel.com ([192.55.52.93]:59147 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756749AbcDEIs2 (ORCPT ); Tue, 5 Apr 2016 04:48:28 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,443,1455004800"; d="scan'208";a="951901980" Date: Tue, 5 Apr 2016 11:48:23 +0300 From: Mika Westerberg To: Linus Walleij Cc: Cristina Ciocan , Mathias Nyman , Heikki Krogerus , "linux-gpio@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Irina Tirdea , Octavian Purdila Subject: Re: [PATCH v4 3/6] pinctrl: baytrail: Update gpio chip operations Message-ID: <20160405084823.GG1727@lahna.fi.intel.com> References: <1459508407-22011-1-git-send-email-cristina.ciocan@intel.com> <1459508407-22011-4-git-send-email-cristina.ciocan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Apr 04, 2016 at 04:08:47PM +0200, Linus Walleij wrote: > On Fri, Apr 1, 2016 at 1:00 PM, Cristina Ciocan > wrote: > > > This patch updates the gpio chip implementation in order to interact with > > the pin control model: the chip contains reference to SOC data and > > pin/group/community information is retrieved through the SOC reference. > > > > Signed-off-by: Cristina Ciocan > > Patch applied with Mika's ACK. Thanks! > Cristina & Mika, can you provide feedback on a patch I sent last week: > http://marc.info/?l=linux-gpio&m=145864063724362&w=2 > > This makes it possible for a GPIO driver to use native > open drain if the hardware supports this instead of relying > on switching the pin to input and thus expecting high impedance. Looks like a good idea to me. Recent Intel hardware (Skylake, Broxton) is capable of taking advantage of this. Not sure if Baytrail supports this at hardware level, though. > With a backing pin control driver I think that maybe we need > a pin control back-end performing things like this on behalf > of the GPIO driver, something like > pinctrl_gpio_set_config(unsigned gpio, enum pin_config_param param, > u16 argument); > > So the pin controller can perform config on behalf of the > GPIO driver (e.g. setting a backing pin to open drain). > > Do you think we will need this? If I understand this right, GPIO part of the pinctrl driver just calls pinctrl_gpio_set_config() with correct parameters in its ->set_single_ended() to get the pin to the right mode. So yes, I think we could use it, at least from Intel pinctrl/GPIO drivers perspective :)