From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932598AbcDNRMY (ORCPT ); Thu, 14 Apr 2016 13:12:24 -0400 Received: from mail.kernel.org ([198.145.29.136]:47908 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932420AbcDNRMW (ORCPT ); Thu, 14 Apr 2016 13:12:22 -0400 Date: Thu, 14 Apr 2016 12:12:15 -0500 From: Rob Herring To: Vignesh R Cc: Tony Lindgren , nsekhar@ti.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 2/2] ARM: dts: dra7x: Support QSPI MODE-0 operation at 64MHz Message-ID: <20160414171215.GA9860@rob-hp-laptop> References: <1460629101-24309-1-git-send-email-vigneshr@ti.com> <1460629101-24309-3-git-send-email-vigneshr@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1460629101-24309-3-git-send-email-vigneshr@ti.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Apr 14, 2016 at 03:48:21PM +0530, Vignesh R wrote: > According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on > DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas > MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better > throughput. > > Signed-off-by: Vignesh R > --- > Documentation/devicetree/bindings/spi/ti_qspi.txt | 7 +++++++ > arch/arm/boot/dts/dra7-evm.dts | 6 ++---- > arch/arm/boot/dts/dra72-evm.dts | 6 ++---- > 3 files changed, 11 insertions(+), 8 deletions(-) > > diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt b/Documentation/devicetree/bindings/spi/ti_qspi.txt > index cc8304aa64ac..50b14f6b53a3 100644 > --- a/Documentation/devicetree/bindings/spi/ti_qspi.txt > +++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt > @@ -19,6 +19,13 @@ Optional properties: > - syscon-chipselects: Handle to system control region contains QSPI > chipselect register and offset of that register. > > +NOTE: TI QSPI controller requires different pinmux and IODelay > +paramaters for Mode-0 and Mode-3 operations, which needs to be set up by > +the bootloader (U-Boot). Default configuration only supports Mode-0 > +operation. Hence, "spi-cpol" and "spi-cpha" DT properties cannot be > +specified in the slave nodes of TI QSPI controller without appropriate > +modification to bootloader. But these properties are properties of what the slave device supports, right? I don't see how you can change them based on the controller. Rob