From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753181AbcDVNQf (ORCPT ); Fri, 22 Apr 2016 09:16:35 -0400 Received: from mail1.bemta14.messagelabs.com ([193.109.254.110]:21332 "EHLO mail1.bemta14.messagelabs.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752031AbcDVNQd (ORCPT ); Fri, 22 Apr 2016 09:16:33 -0400 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrHIsWRWlGSWpSXmKPExsUSt3Opsa62ilS 4QesBJYsrFw8xWUx9+ITN4tuVDiaLy7vmsFl07upntdjwfS2jA5vHhs9NbB47Z91l99i0qpPN Y9/bZWwe67dcZfH4vEkugC2KNTMvKb8igTXj7MXVTAWzFCp6H2xhbGCcJtPFyMUhJLCeUeL/l PmMXYycQE6FxIKuvcwgNpuAhcTkEw/YQGwWAVWJ1fN7weLCAoESzV1TGUGaRQS6GCVWv3rMDp JgFiiXOLtpEVgDr4CDxKWGWUwQtqDEyZlPWCBqJCQOvnjBDLHMQOL0gkawuISAvcT091eB4hx Atr5E47FYiLChxPdZ31ggwuYS7d+FJzDyz0IydBaSoQsYmVYxahSnFpWlFukamuklFWWmZ5Tk Jmbm6BoamujlphYXJ6an5iQmFesl5+duYgSGcz0DA+MOxq+nPQ8xSnIwKYnynn8gGS7El5SfU pmRWJwRX1Sak1p8iFGGg0NJgrdIWSpcSLAoNT21Ii0zBxhZMGkJDh4lEV4PkDRvcUFibnFmOk TqFKOilDhvAUhCACSRUZoH1waL5kuMslLCvIwMDAxCPAWpRbmZJajyrxjFORiVhHmtQKbwZOa VwE1/BbSYCWjxvwuSIItLEhFSUg2M9hrz7SUaHBf/SYkIWLPFeBkT3+XmcMtpapnF+vdnOSZ+ LDhc3vj8m2rLoZ/PpP0jXp54+/Ja19lFVYwm7365qa5b16ySVSRq67FoarnvsfeCz8Ti0h3v7 Z+iukZv0vKU2pO7t+cWGV2/wXVlpYLuc2ONFdonnky/dNpeU93DPfPyzD9bb/4+o8RSnJFoqM VcVJwIAO/L6dThAgAA X-Env-Sender: Adam.Thomson.Opensource@diasemi.com X-Msg-Ref: server-15.tower-193.messagelabs.com!1461330987!32374831!1 X-Originating-IP: [94.185.165.51] X-StarScan-Received: X-StarScan-Version: 8.28; banners=-,-,- X-VirusChecked: Checked From: Adam Thomson Date: Fri, 22 Apr 2016 14:16:26 +0100 Subject: [PATCH] ASoC: da7218: Update PLL ranges and dividers to improve locking To: Mark Brown , Liam Girdwood , Jaroslav Kysela , Takashi Iwai CC: , , Support Opensource Message-ID: <20160422131626.CB01C3FA9D@swsrvapps-01.diasemi.com> MIME-Version: 1.0 Content-Type: text/plain X-KSE-AttachmentFiltering-Interceptor-Info: protection disabled X-KSE-ServerInfo: sw-ex-cashub01.diasemi.com, 9 X-KSE-Antivirus-Interceptor-Info: scan successful X-KSE-Antivirus-Info: Clean, bases: 22/04/2016 06:52:00 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The expected MCLK frequency ranges and the associated dividers are updated to improve PLL locking in a corner scenario, with low MCLK frequency near an input divider change boundary. Signed-off-by: Adam Thomson --- This patch is based on v4.6-rc1 kernel version sound/soc/codecs/da7218.c | 32 ++++++++++++++++---------------- sound/soc/codecs/da7218.h | 21 ++++++++++++--------- 2 files changed, 28 insertions(+), 25 deletions(-) diff --git a/sound/soc/codecs/da7218.c b/sound/soc/codecs/da7218.c index 93575f2..99ce23e 100644 --- a/sound/soc/codecs/da7218.c +++ b/sound/soc/codecs/da7218.c @@ -1868,27 +1868,27 @@ static int da7218_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, /* Verify 32KHz, 2MHz - 54MHz MCLK provided, and set input divider */ if (da7218->mclk_rate == 32768) { - indiv_bits = DA7218_PLL_INDIV_2_5_MHZ; - indiv = DA7218_PLL_INDIV_2_10_MHZ_VAL; + indiv_bits = DA7218_PLL_INDIV_9_TO_18_MHZ; + indiv = DA7218_PLL_INDIV_9_TO_18_MHZ_VAL; } else if (da7218->mclk_rate < 2000000) { dev_err(codec->dev, "PLL input clock %d below valid range\n", da7218->mclk_rate); return -EINVAL; - } else if (da7218->mclk_rate <= 5000000) { - indiv_bits = DA7218_PLL_INDIV_2_5_MHZ; - indiv = DA7218_PLL_INDIV_2_10_MHZ_VAL; - } else if (da7218->mclk_rate <= 10000000) { - indiv_bits = DA7218_PLL_INDIV_5_10_MHZ; - indiv = DA7218_PLL_INDIV_2_10_MHZ_VAL; - } else if (da7218->mclk_rate <= 20000000) { - indiv_bits = DA7218_PLL_INDIV_10_20_MHZ; - indiv = DA7218_PLL_INDIV_10_20_MHZ_VAL; - } else if (da7218->mclk_rate <= 40000000) { - indiv_bits = DA7218_PLL_INDIV_20_40_MHZ; - indiv = DA7218_PLL_INDIV_20_40_MHZ_VAL; + } else if (da7218->mclk_rate <= 4500000) { + indiv_bits = DA7218_PLL_INDIV_2_TO_4_5_MHZ; + indiv = DA7218_PLL_INDIV_2_TO_4_5_MHZ_VAL; + } else if (da7218->mclk_rate <= 9000000) { + indiv_bits = DA7218_PLL_INDIV_4_5_TO_9_MHZ; + indiv = DA7218_PLL_INDIV_4_5_TO_9_MHZ_VAL; + } else if (da7218->mclk_rate <= 18000000) { + indiv_bits = DA7218_PLL_INDIV_9_TO_18_MHZ; + indiv = DA7218_PLL_INDIV_9_TO_18_MHZ_VAL; + } else if (da7218->mclk_rate <= 36000000) { + indiv_bits = DA7218_PLL_INDIV_18_TO_36_MHZ; + indiv = DA7218_PLL_INDIV_18_TO_36_MHZ_VAL; } else if (da7218->mclk_rate <= 54000000) { - indiv_bits = DA7218_PLL_INDIV_40_54_MHZ; - indiv = DA7218_PLL_INDIV_40_54_MHZ_VAL; + indiv_bits = DA7218_PLL_INDIV_36_TO_54_MHZ; + indiv = DA7218_PLL_INDIV_36_TO_54_MHZ_VAL; } else { dev_err(codec->dev, "PLL input clock %d above valid range\n", da7218->mclk_rate); diff --git a/sound/soc/codecs/da7218.h b/sound/soc/codecs/da7218.h index c2c5904..477cd37 100644 --- a/sound/soc/codecs/da7218.h +++ b/sound/soc/codecs/da7218.h @@ -876,15 +876,11 @@ /* DA7218_PLL_CTRL = 0x91 */ #define DA7218_PLL_INDIV_SHIFT 0 #define DA7218_PLL_INDIV_MASK (0x7 << 0) -#define DA7218_PLL_INDIV_2_5_MHZ (0x0 << 0) -#define DA7218_PLL_INDIV_5_10_MHZ (0x1 << 0) -#define DA7218_PLL_INDIV_10_20_MHZ (0x2 << 0) -#define DA7218_PLL_INDIV_20_40_MHZ (0x3 << 0) -#define DA7218_PLL_INDIV_40_54_MHZ (0x4 << 0) -#define DA7218_PLL_INDIV_2_10_MHZ_VAL 2 -#define DA7218_PLL_INDIV_10_20_MHZ_VAL 4 -#define DA7218_PLL_INDIV_20_40_MHZ_VAL 8 -#define DA7218_PLL_INDIV_40_54_MHZ_VAL 16 +#define DA7218_PLL_INDIV_2_TO_4_5_MHZ (0x0 << 0) +#define DA7218_PLL_INDIV_4_5_TO_9_MHZ (0x1 << 0) +#define DA7218_PLL_INDIV_9_TO_18_MHZ (0x2 << 0) +#define DA7218_PLL_INDIV_18_TO_36_MHZ (0x3 << 0) +#define DA7218_PLL_INDIV_36_TO_54_MHZ (0x4 << 0) #define DA7218_PLL_MCLK_SQR_EN_SHIFT 4 #define DA7218_PLL_MCLK_SQR_EN_MASK (0x1 << 4) #define DA7218_PLL_MODE_SHIFT 6 @@ -1336,6 +1332,13 @@ #define DA7218_PLL_FREQ_OUT_90316 90316800 #define DA7218_PLL_FREQ_OUT_98304 98304000 +/* PLL Frequency Dividers */ +#define DA7218_PLL_INDIV_2_TO_4_5_MHZ_VAL 1 +#define DA7218_PLL_INDIV_4_5_TO_9_MHZ_VAL 2 +#define DA7218_PLL_INDIV_9_TO_18_MHZ_VAL 4 +#define DA7218_PLL_INDIV_18_TO_36_MHZ_VAL 8 +#define DA7218_PLL_INDIV_36_TO_54_MHZ_VAL 16 + /* ALC Calibration */ #define DA7218_ALC_CALIB_DELAY_MIN 2500 #define DA7218_ALC_CALIB_DELAY_MAX 5000 -- 1.9.3