From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756009AbcECLcR (ORCPT ); Tue, 3 May 2016 07:32:17 -0400 Received: from mezzanine.sirena.org.uk ([106.187.55.193]:44372 "EHLO mezzanine.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755489AbcECLcP (ORCPT ); Tue, 3 May 2016 07:32:15 -0400 Date: Tue, 3 May 2016 12:32:00 +0100 From: Mark Brown To: Crestez Dan Leonard Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler , Daniel Baluta , Ge Gao , Peter Rosin Message-ID: <20160503113200.GN6292@sirena.org.uk> References: <20160502152328.GG6292@sirena.org.uk> <572889C4.40806@intel.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="YuJye9aIuN0w6xGV" Content-Disposition: inline In-Reply-To: <572889C4.40806@intel.com> X-Cookie: Use in well-ventilated area. User-Agent: Mutt/1.6.0 (2016-04-01) X-SA-Exim-Connect-IP: 2a01:348:6:8808:fab::3 X-SA-Exim-Mail-From: broonie@sirena.org.uk Subject: Re: [RFC 0/7] iio: inv_mpu6050: Support i2c master and external readings X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --YuJye9aIuN0w6xGV Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, May 03, 2016 at 02:21:40PM +0300, Crestez Dan Leonard wrote: > I have a device which has several registers with bits that are a mix of > "cacheable" and "volatile". For example for register SLV4_CTRL: > - Bit 7 (I2C_SLV4_EN) triggers a transaction with slave 4 when a "1" is > written. The bit is cleared when the transaction is done. > - Bits 0-4 (I2C_MST_DLY) configures the reduced access rate of I2C > slaves relative to the device sample rate. This applies to slaves 0-3 as > well. > If I2C_MST_DLY was a separate register it could be easily cached by > regmap. Because it's part of a volatile register I have to add a > private_data field caching the value and always write it when triggering > a SLV4 transfer. > Jonathan was wondering if regmap can still be used somehow instead of > custom caching. If you want to cache in regmap just write a 0 back to the enable bit after you've set it. --YuJye9aIuN0w6xGV Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAEBCAAGBQJXKIwvAAoJECTWi3JdVIfQ4jYH+gPdHHhwr8Z9oMSAwvGg9u4B 2HkhyrcABJQxFwoowrHADUQC/NZ4WMOpO1hVAnz9XXA2+LU71WXk3n5s/aaRaIPl EHa4C91kitZvHK4+++4l2n9rihFQ0jiND1/2Z7ufHnDXROHm7/wAGfXUbUWQJekZ NtVwsjn99TruSGtIB7IH9bv1zmIJu2tCCN1Zb9Z6SHbSsLlT7DojK5vnBnvCEyaj DaCH9qyj0eDcq58CR9WVQJ9synFKm1/dHJvboWtIrjCF/nLYk/2GHEDimjZJRCJU xAR6jBfFTTw+IhC9SJ9Aee29WpeJRiHY6gcPU8wn4cHeyteSJ6h+AeHpCFwdc9w= =/q4l -----END PGP SIGNATURE----- --YuJye9aIuN0w6xGV--