From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755799AbcEYCMc (ORCPT ); Tue, 24 May 2016 22:12:32 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:49517 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752179AbcEYCMb (ORCPT ); Tue, 24 May 2016 22:12:31 -0400 Message-Id: <201605250212.u4P28ued046877@mx0a-001b2d01.pphosted.com> X-IBM-Helo: d28dlp01.in.ibm.com X-IBM-MailFrom: shreyas@linux.vnet.ibm.com X-IBM-RcptTo: linux-kernel@vger.kernel.org Date: Wed, 25 May 2016 07:42:17 +0530 From: Shreyas B Prabhu User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.1.0 MIME-Version: 1.0 To: Madhavan Srinivasan , mpe@ellerman.id.au CC: linuxppc-dev@lists.ozlabs.org, paulus@ozlabs.org, linux-kernel@vger.kernel.org, mikey@neuling.org, ego@linux.vnet.ibm.com Subject: Re: [PATCH v3 7/9] powerpc/powernv: Add platform support for stop instruction References: <1464016722-7488-1-git-send-email-shreyas@linux.vnet.ibm.com> <1464016722-7488-8-git-send-email-shreyas@linux.vnet.ibm.com> <886163be-b915-b60f-b25b-bf770f3ed821@linux.vnet.ibm.com> In-Reply-To: <886163be-b915-b60f-b25b-bf770f3ed821@linux.vnet.ibm.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16052502-0012-0000-0000-00000281DB78 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 16052502-0013-0000-0000-00000CC75D31 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-05-25_01:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=8 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1604210000 definitions=main-1605250022 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 05/24/2016 02:17 PM, Madhavan Srinivasan wrote: > > > On Monday 23 May 2016 08:48 PM, Shreyas B. Prabhu wrote: >> POWER ISA v3 defines a new idle processor core mechanism. In summary, >> a) new instruction named stop is added. This instruction replaces >> instructions like nap, sleep, rvwinkle. >> b) new per thread SPR named PSSCR is added which controls the behavior >> of stop instruction. > > Kindly expand the register name at first use like > Processor Stop Status and Control Register (PSSCR) > >> >> PSSCR has following key fields > > Having the PSSCR layout here will help? something like this > > ---------------------------------------------------------- > | PLS | /// | SD | ESL | EC | PSLL | /// | TR | MTL | RL | > ---------------------------------------------------------- > 0 4 41 42 43 44 48 54 56 60 > >> Bits 0:3 - Power-Saving Level Status. This field indicates the lowest >> power-saving state the thread entered since stop instruction was last >> executed. >> >> Bit 42 - Enable State Loss >> 0 - No state is lost irrespective of other fields >> 1 - Allows state loss >> >> Bits 44:47 - Power-Saving Level Limit >> This limits the power-saving level that can be entered into. >> >> Bits 60:63 - Requested Level >> Used to specify which power-saving level must be entered on executing >> stop instruction >> >> This patch adds support for stop instruction and PSSCR handling. >> >> Signed-off-by: Shreyas B. Prabhu >> --- Hi Madhavan, Thanks for the review. I have incorporated your review comments in v4. Thanks, Shreyas