From: Mark Brown <broonie@kernel.org>
To: Meng Yi <meng.yi@nxp.com>
Cc: "dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>,
David Airlie <airlied@linux.ie>, Stefan Agner <stefan@agner.ch>,
"airlied@redhat.com" <airlied@redhat.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: fsl-dcu not works on latest "drm-next"
Date: Wed, 25 May 2016 11:41:03 +0100 [thread overview]
Message-ID: <20160525104103.GV8206@sirena.org.uk> (raw)
In-Reply-To: <HE1PR04MB1051016E918C26EABD7B30C9EC400@HE1PR04MB1051.eurprd04.prod.outlook.com>
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On Wed, May 25, 2016 at 09:59:39AM +0000, Meng Yi wrote:
Please fix your mail client to word wrap within paragraphs at something
substantially less than 80 columns. Doing this makes your messages much
easier to read and reply to.
> I read out the value of relevant register using "CodeWarrior TAP", find that endianness is not right.
> Then I changed endianness of the value to be written that using " regmap_write" . It works.
> But "regmap_update_bits" still have the problem.
> I had checked log of regmap, and didn't find which commit caused that.
You've not specifically described the problem here - what are the
endiannesses of both the CPU and the device you're talking to? What
specifically is the endianess problem you are seeing, what are you
seeing and what do you expect to see?
> I am not familiar with regmap, can you give some advices?
Is the device described in the DT or regmap_config as having the
endianess that it actually has?
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next prev parent reply other threads:[~2016-05-25 10:41 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <HE1PR04MB105158F9CB2CEC73E6B5F5E9EC7A0@HE1PR04MB1051.eurprd04.prod.outlook.com>
2016-05-25 2:14 ` Meng Yi
2016-05-25 6:20 ` Stefan Agner
2016-05-25 8:32 ` Alexander Stein
2016-05-25 8:58 ` Meng Yi
2016-05-25 9:57 ` Alexander Stein
2016-05-25 10:25 ` Meng Yi
2016-05-25 12:16 ` Alexander Stein
2016-05-26 8:18 ` Meng Yi
2016-05-26 9:11 ` Alexander Stein
2016-05-25 9:18 ` Mark Brown
2016-05-25 9:59 ` Meng Yi
2016-05-25 10:41 ` Mark Brown [this message]
2016-05-26 8:23 ` Meng Yi
2016-05-26 9:11 ` Alexander Stein
2016-05-27 5:54 ` Stefan Agner
2016-05-27 12:20 ` Mark Brown
2016-05-27 17:36 ` Stefan Agner
2016-05-27 19:50 ` Mark Brown
2016-06-03 22:52 ` Stefan Agner
2016-06-07 2:16 ` Meng Yi
2016-06-07 2:46 ` Stefan Agner
2016-06-07 3:47 ` Meng Yi
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