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Date: Thu, 26 May 2016 17:44:57 +0100
From: Catalin Marinas <catalin.marinas@arm.com>
To: Russell King - ARM Linux <linux@armlinux.org.uk>
Cc: Mark Rutland <mark.rutland@arm.com>, Hanjun Guo <guohanjun@huawei.com>,
        Benjamin Herrenschmidt <benh@kernel.crashing.org>,
        "Leizhen (ThunderTown)" <thunder.leizhen@huawei.com>,
        Will Deacon <will.deacon@arm.com>,
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        Paul Mackerras <paulus@samba.org>,
        Michael Ellerman <mpe@ellerman.id.au>,
        Tianhong Ding <dingtianhong@huawei.com>,
        linux-arm-kernel <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 1/1] arm64: fix flush_cache_range
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On Wed, May 25, 2016 at 06:27:07PM +0100, Russell King - ARM Linux wrote:
> On Wed, May 25, 2016 at 04:22:55PM +0100, Catalin Marinas wrote:
> > That's when we realised that the CoW problem no longer exists for
> > non-aliasing VIPT caches. However, the I-cache counterpart 6060e8df5178
> > has not been reverted.
> 
> I think I mostly agree, except for reverting 6060e8df5178, which I don't
> think would be correct.  That reintroduces the possibility of flushing
> the I-cache twice in that path, once for aliasing vipt dcaches, and again
> for asid tagged vivt icaches.  I'd rather have the code structured so we
> only do this once.

__sync_icache_dcache() seems to take care of AIVIVT caches as well (i.e.
it invalidates the whole I-cache) so I think we could just remove the
__flush_icache_all() from flush_cache_range().

I can't find a scenario where we still need D-cache clean+invalidate in
flush_cache_range() for aliasing VIPT. As for the I-cache,
__sync_icache_dcache() takes care of all the aliases.

-- 
Catalin