From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754717AbcEZRJL (ORCPT ); Thu, 26 May 2016 13:09:11 -0400 Received: from bombadil.infradead.org ([198.137.202.9]:57759 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751497AbcEZRJJ (ORCPT ); Thu, 26 May 2016 13:09:09 -0400 Date: Thu, 26 May 2016 10:09:11 -0700 From: Darren Hart To: Rajneesh Bhardwaj Cc: platform-driver-x86@vger.kernel.org, andriy.shevchenko@linux.intel.com, linux-kernel@vger.kernel.org, olof@lixom.net, tglx@linutronix.de, hpa@zytor.com, dbasehore@google.com, vishwanath.somayaji@intel.com Subject: Re: [PATCH v7] platform:x86: Add PMC Driver for Intel Core SoC Message-ID: <20160526170911.GA98596@f23x64.localdomain> References: <1464253879-18504-1-git-send-email-rajneesh.bhardwaj@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1464253879-18504-1-git-send-email-rajneesh.bhardwaj@intel.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 26, 2016 at 02:41:19PM +0530, Rajneesh Bhardwaj wrote: > This patch adds the Power Management Controller driver as a PCI driver > for Intel Core SoC architecture. > > This driver can utilize debugging capabilities and supported features > as exposed by the Power Management Controller. > > Please refer to the below specification for more details on PMC features. > http://www.intel.in/content/www/in/en/chipsets/100-series-chipset-datasheet-vol-2.html > > The current version of this driver exposes SLP_S0_RESIDENCY counter. > This counter can be used for detecting fragile SLP_S0 signal related > failures and take corrective actions when PCH SLP_S0 signal is not > asserted after kernel freeze as part of suspend to idle flow > (echo freeze > /sys/power/state). > > Intel Platform Controller Hub (PCH) asserts SLP_S0 signal when it > detects favorable conditions to enter its low power mode. As a > pre-requisite the SoC should be in deepest possible Package C-State > and devices should be in low power mode. For example, on Skylake SoC > the deepest Package C-State is Package C10 or PC10. Suspend to idle > flow generally leads to PC10 state but PC10 state may not be sufficient > for realizing the platform wide power potential which SLP_S0 signal > assertion can provide. > > SLP_S0 signal is often connected to the Embedded Controller (EC) and the > Power Management IC (PMIC) for other platform power management related > optimizations. > > In general, SLP_S0 assertion == PC10 + PCH low power mode + ModPhy Lanes > power gated + PLL Idle. > > As part of this driver, a mechanism to read the SLP_S0_RESIDENCY is exposed > as an API and also debugfs features are added to indicate SLP_S0 signal > assertion residency in microseconds. > > echo freeze > /sys/power/state > wake the system > cat /sys/kernel/debug/pmc_core/slp_s0_residency_usec > > Signed-off-by: Rajneesh Bhardwaj > Signed-off-by: Vishwanath Somayaji Queued for 4.7. Thank you. -- Darren Hart Intel Open Source Technology Center