From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933003AbcE3Jgt (ORCPT ); Mon, 30 May 2016 05:36:49 -0400 Received: from mail-wm0-f51.google.com ([74.125.82.51]:35178 "EHLO mail-wm0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932632AbcE3Jgr (ORCPT ); Mon, 30 May 2016 05:36:47 -0400 Date: Mon, 30 May 2016 11:36:42 +0200 From: Daniel Vetter To: Jose Abreu Cc: Daniel Vetter , "dri-devel@lists.freedesktop.org" , "linux-kernel@vger.kernel.org" , Alexey.Brodkin@synopsys.com Subject: Re: DRM DMA Engine Message-ID: <20160530093642.GH27098@phenom.ffwll.local> Mail-Followup-To: Jose Abreu , "dri-devel@lists.freedesktop.org" , "linux-kernel@vger.kernel.org" , Alexey.Brodkin@synopsys.com References: <5745C8C7.1090906@synopsys.com> <20160526080600.GP27098@phenom.ffwll.local> <574BFD61.60101@synopsys.com> <574C0148.3090504@synopsys.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <574C0148.3090504@synopsys.com> X-Operating-System: Linux phenom 4.6.0-rc5+ User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, May 30, 2016 at 10:00:56AM +0100, Jose Abreu wrote: > ++ Daniel > > > On 30-05-2016 09:44, Jose Abreu wrote: > > Hi Daniel, > > > > Thanks for your answer. > > > > On 26-05-2016 09:06, Daniel Vetter wrote: > >> On Wed, May 25, 2016 at 04:46:15PM +0100, Jose Abreu wrote: > >>> Hi all, > >>> > >>> Currently I am trying to develop a DRM driver that will use > >>> Xilinx VDMA to transfer video data to a HDMI TX Phy and I am > >>> facing a difficulty regarding the understanding of the DRM DMA > >>> Engine. I looked at several sources and at the DRM core source > >>> but the flow of creating and interfacing with the DMA controller > >>> is still not clear to me. > >>> > >>> At DRI web page the X server is mentioned. Does it mean that the > >>> channel creation and handling is done by the X server? If so, > >>> what is the DRM driver responsible to do then and what exactly > >>> does the DRM core do? As I am using Xilinx VDMA do you foresee > >>> any special implementation details? > >>> > >>> Just for reference here is the description of the Xilinx VDMA: > >>> "The Advanced eXtensible Interface Video Direct Memory Access > >>> (AXI VDMA) core is a soft Xilinx Intellectual Property (IP) core > >>> providing high-bandwidth direct memory access between memory and > >>> AXI4-Stream video type target peripherals including peripherals > >>> which support AXI4-Stream Video Protocol." The driver is > >>> available at "drivers/dma/xilinx/xilinx_vdma.c". > >>> > >>> Another important point: I am using PCI Express connected to a > >>> FPGA which has all the necessary components (Xilinx VDMA, I2S, > >>> ...) and the HDMI TX Phy. > >>> > >>> Looking forward to you help. > >> If your dma engine is just for HDMI display, forget all the stuff you find > >> about DRI and X server on the various wikis. That's for opengl rendering. > >> > >> The only thing you need is a kernel-modesetting driver, and nowadays those > >> are written using the atomic modeset framework. There's plenty of > >> introductory talks and stuff all over the web (I suggest the latest > >> version of Laurent Pinchart's talk as a good starting point). > >> -Daniel > > I watched the talk of Laurent and I already have a simple KMS > > driver with an encoder (which is bridge dw-hdmi), a connector and > > a crtc. My doubt now is how do I setup the video path so that > > video samples are sent using the Xilinx VDMA to our hdmi phy. > > > > Sorry if I am making some mistake (I am quite new to DRM and DMA) > > but here is my thoughts: > > - A DMA channel or some kind of mapping must be done so that > > the DRM driver knows where to send samples; > > - The Xilinx VDMA driver must be instantiated (which I am > > already doing); > > - Some kind of association between the DRM DMA engine and > > Xilinx VDMA must be done; > > - A callback should exist that is called on each frame and > > updates the data that is sent to Xilinx VDMA. > > > > Does this looks okay to you or am I missing something? I still > > haven't figured out how should I associate the VDMA to the DRM > > DMA engine and how should I map the DMA to the DRM driver. > > > > Can you give me some help or refer me to someone who can? Also, > > is there a DRM driver that uses a similar architecture? I assume that xilinx VDMA is the only way to feed pixel data into your display pipeline. Under that assumption: drm_plane should map to Xilinx VDMA, and the drm_plane->drm_crtc link would represent the dma channel. With atomic you can subclass drm_plane/crtc_state structures to store all the runtime configuration in there. The actual buffer itsel would be represented by a drm_framebuffer, which either wraps a shmem gem or a cma gem object. If you want to know about the callbacks used by the atomic helpers to push out plane updates, look at the hooks drm_atomic_helper_commit_planes() (and the related functions, see kerneldoc) calls. I hope this helps a bit more. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch