From: Peter Zijlstra <peterz@infradead.org>
To: Lukasz Odzioba <lukasz.odzioba@intel.com>
Cc: linux-kernel@vger.kernel.org, x86@kernel.org, tglx@linutronix.de,
mingo@redhat.com, hpa@zytor.com, ak@linux.intel.com,
kan.liang@intel.com, akpm@linux-foundation.org,
eranian@google.com, acme@kernel.org,
alexander.shishkin@linux.intel.com, bp@suse.de,
lukasz.anaczkowski@intel.com
Subject: Re: [PATCH 1/1] perf/x86/intel: Add extended event constraints for Knights Landing
Date: Wed, 8 Jun 2016 08:48:00 +0200 [thread overview]
Message-ID: <20160608064800.GN30154@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <1465358536-21544-1-git-send-email-lukasz.odzioba@intel.com>
On Wed, Jun 08, 2016 at 06:02:16AM +0200, Lukasz Odzioba wrote:
> For Knights Landing processor we need to filter OFFCORE_RESPONSE
> events by config1 parameter to make sure that it will end up in
> an appropriate PMC to meet specification.
>
> On Knights Landing:
> MSR_OFFCORE_RSP_1 bits 8, 11, 14 can be used only on PMC1
> MSR_OFFCORE_RSP_0 bit 38 can be used only on PMC0
>
> This patch introduces INTEL_EEVENT_CONSTRAINT where third parameter
> specifies extended config bits allowed only on given PMCs.
>
How does this work in the light of intel_alt_er() ?
next prev parent reply other threads:[~2016-06-08 6:48 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-08 4:02 Lukasz Odzioba
2016-06-08 6:48 ` Peter Zijlstra [this message]
2016-06-20 10:26 ` Odzioba, Lukasz
2016-06-21 9:37 ` Peter Zijlstra
2016-06-24 14:54 ` Odzioba, Lukasz
2016-06-24 17:04 ` Stephane Eranian
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