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Date: Wed, 8 Jun 2016 15:29:00 -0500
From: Rob Herring <robh@kernel.org>
To: Shawn Lin <shawn.lin@rock-chips.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>, linux-kernel@vger.kernel.org,
        linux-rockchip@lists.infradead.org, Heiko Stuebner <heiko@sntech.de>,
        Doug Anderson <dianders@chromium.org>,
        Wenrui Li <wenrui.li@rock-chips.com>, devicetree@vger.kernel.org
Subject: Re: [PATCH 1/2] Documentation: bindings: add dt documentation for
 Rockchip PCIe PHY
Message-ID: <20160608202900.GA25662@rob-hp-laptop>
References: <1465370708-23619-1-git-send-email-shawn.lin@rock-chips.com>
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gOn Wed, Jun 08, 2016 at 03:25:08PM +0800, Shawn Lin wrote:
> This patch adds a binding that describes the Rockchip PCIe PHY
> found on Rockchip SoCs PCIe interface.
> 
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
> 
>  .../devicetree/bindings/phy/rockchip-pcie-phy.txt  | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> new file mode 100644
> index 0000000..ba8c406
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> @@ -0,0 +1,22 @@
> +Rockchip PCIE PHY
> +-----------------------
> +
> +Required properties:
> + - compatible: rockchip,rk3399-pcie-phy
> + - #phy-cells: must be 0
> +
> +Example:
> +
> +grf: syscon@ff770000 {
> +	compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	...
> +
> +	pcie_phy: phy@e220 {

unit-address needs a reg property or drop the unit address. I'd do the 
former if there's a register range you can describe here.


> +		compatible = "rockchip,rk3399-pcie-phy";
> +		#phy-cells = <0>;
> +	};
> +};
> +
> -- 
> 2.3.7
> 
>