From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934189AbcFIHmi (ORCPT ); Thu, 9 Jun 2016 03:42:38 -0400 Received: from smtp5-g21.free.fr ([212.27.42.5]:5150 "EHLO smtp5-g21.free.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751760AbcFIHmg convert rfc822-to-8bit (ORCPT ); Thu, 9 Jun 2016 03:42:36 -0400 Date: Thu, 9 Jun 2016 09:42:19 +0200 From: Jean-Francois Moine To: Maxime Ripard Cc: Mike Turquette , Stephen Boyd , Chen-Yu Tsai , linux-clk@vger.kernel.org, Hans de Goede , Andre Przywara , Rob Herring , Vishnu Patekar , linux-arm-kernel@lists.infradead.org, Boris Brezillon , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 14/15] clk: sunxi-ng: Add H3 clocks Message-Id: <20160609094219.6b4153aed49fb5ab6ccd7f74@free.fr> In-Reply-To: <20160607204154.31967-15-maxime.ripard@free-electrons.com> References: <20160607204154.31967-1-maxime.ripard@free-electrons.com> <20160607204154.31967-15-maxime.ripard@free-electrons.com> X-Mailer: Sylpheed 3.5.0 (GTK+ 2.24.30; armv7l-unknown-linux-gnueabihf) Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 7 Jun 2016 22:41:53 +0200 Maxime Ripard wrote: > Add the list of clocks and resets found in the H3 CCU. > > Signed-off-by: Maxime Ripard > > --- > Changes from v1: > - Only build the H3 clocks description when MACH_SUN8I is set > --- > drivers/clk/sunxi-ng/Makefile | 2 + > drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 703 +++++++++++++++++++++++++++++++++++ > include/dt-bindings/clock/sun8i-h3.h | 162 ++++++++ > include/dt-bindings/reset/sun8i-h3.h | 103 +++++ > 4 files changed, 970 insertions(+) > create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-h3.c > create mode 100644 include/dt-bindings/clock/sun8i-h3.h > create mode 100644 include/dt-bindings/reset/sun8i-h3.h > > diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile > index ddcf456df719..cafabf0e8060 100644 > --- a/drivers/clk/sunxi-ng/Makefile > +++ b/drivers/clk/sunxi-ng/Makefile > @@ -13,3 +13,5 @@ obj-y += ccu_nkm.o > obj-y += ccu_nkmp.o > obj-y += ccu_nm.o > obj-y += ccu_phase.o > + > +obj-$(CONFIG_MACH_SUN8I) += ccu-sun8i-h3.o > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c > new file mode 100644 > index 000000000000..41102ac020d9 > --- /dev/null > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c [snip] > +static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = { > + .clks = sun8i_h3_ccu_clks, > + .num_clks = ARRAY_SIZE(sun8i_h3_ccu_clks), > + > + .resets = sun8i_h3_ccu_resets, > + .num_resets = ARRAY_SIZE(sun8i_h3_ccu_resets), > +}; > + > +#define SUN8I_H3_PLL2_REG 0x008 SUN8I_H3_PLL_AUDIO_REG would be clearer. This definition could go near the audio PLL description with some comments. > + > +static void __init sun8i_h3_ccu_setup(struct device_node *node) > +{ > + void __iomem *reg; > + u32 val; > + > + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); > + if (IS_ERR(reg)) { > + pr_err("%s: Could not map the clock registers\n", > + of_node_full_name(node)); > + return; > + } > + > + /* Force the PLL2-1x divider to 4 */ > + val = readl(reg + SUN8I_H3_PLL2_REG); > + val &= ~GENMASK(4, 0); > + writel(val | 3, reg + SUN8I_H3_PLL2_REG); > + > + sunxi_ccu_probe(node, reg, &sun8i_h3_ccu_desc); > +} > +CLK_OF_DECLARE(sun8i_h3_ccu, "allwinner,sun8i-h3-ccu", > + sun8i_h3_ccu_setup); > diff --git a/include/dt-bindings/clock/sun8i-h3.h b/include/dt-bindings/clock/sun8i-h3.h > new file mode 100644 > index 000000000000..96eced56e7a2 > --- /dev/null > +++ b/include/dt-bindings/clock/sun8i-h3.h [snip] -- Ken ar c'hentań | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/