From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755459AbcFQJ7E (ORCPT ); Fri, 17 Jun 2016 05:59:04 -0400 Received: from mail-by2on0053.outbound.protection.outlook.com ([207.46.100.53]:49984 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753362AbcFQJ66 (ORCPT ); Fri, 17 Jun 2016 05:58:58 -0400 X-Greylist: delayed 101447 seconds by postgrey-1.27 at vger.kernel.org; Fri, 17 Jun 2016 05:58:58 EDT Authentication-Results: spf=none (sender IP is 165.204.84.22) smtp.mailfrom=amd.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=permerror action=none header.from=amd.com; Date: Fri, 17 Jun 2016 18:03:07 +0800 From: Huang Rui To: Vince Weaver CC: Borislav Petkov , Thomas Gleixner , "Peter Zijlstra" , Ingo Molnar , "Andy Lutomirski" , Robert Richter , "Jacob Shin" , Arnaldo Carvalho de Melo , Kan Liang , , , Suravee Suthikulpanit , Aravind Gopalakrishnan , Borislav Petkov , Guenter Roeck , Fengguang Wu Subject: Re: [REDO PATCH v7] perf/x86/amd/power: Add AMD accumulated power reporting mechanism Message-ID: <20160617100306.GB13900@hr-amur2> References: <1457502306-2559-1-git-send-email-ray.huang@amd.com> <20160616053802.GA7810@hr-amur2> MIME-Version: 1.0 Content-Type: text/plain; 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In theory this should also work on an amd fam16h model 30h > > > processor too, correct? The current code limits things to fam15h > > > even though the fam16mod30h has all the proper cpuid flags. > > > > > > > I was told this feature would be supported on fam15h 60h, 70h and > > later processors before. Just checked the fam16h model 30h BKDG, yes, > > it should be also supported. But I didn't test that platform, if you > > confirm it works in your side. We can enable it. > > I can confirm I get power readings on my fam16hmod30h board once I apply a > trivial patch to the driver. I'll send the patch in a separate e-mail. > OK, thanks. > > PTSC's frequency is about 100Mhz, it shouldn't be overflow. > > That's what I thought. I'm trying to read the value using the /dev/msr > interface from userspace and I get weird results. > > i.e.: > Jx: read 62d299b84 > PTSC MSR: read 72fe92 > > sleep 5ms > > Jy: read 631b453b9 > PTSC MSR: read 46b25 > > this happens about half the time (PTSC going backwards). Though > admittedly the problem could somehow be in the MSR code I'm using. > Can you try to read the MSR value two times with the same core (rdmsrl_on_cpu)? Thanks, Rui