From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752872AbcFTQdW (ORCPT ); Mon, 20 Jun 2016 12:33:22 -0400 Received: from vps0.lunn.ch ([178.209.37.122]:52822 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752080AbcFTQdN (ORCPT ); Mon, 20 Jun 2016 12:33:13 -0400 Date: Mon, 20 Jun 2016 18:30:53 +0200 From: Andrew Lunn To: Vivien Didelot Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@savoirfairelinux.com, "David S. Miller" , Florian Fainelli , Ben Dooks , Sergei Shtylyov Subject: Re: [PATCH v4 net-next v4 14/14] net: dsa: mv88e6xxx: abstract switch registers accesses Message-ID: <20160620163053.GE22920@lunn.ch> References: <20160620160337.2934-1-vivien.didelot@savoirfairelinux.com> <20160620160337.2934-15-vivien.didelot@savoirfairelinux.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20160620160337.2934-15-vivien.didelot@savoirfairelinux.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jun 20, 2016 at 12:03:37PM -0400, Vivien Didelot wrote: > When the SMI address of the switch chip is zero, the chip assumes to be > the only one on the SMI master bus and thus responds to all its known > SMI devices addresses (port registers, Global2, etc.) > > When its SMI address is not zero, some chips (e.g. 88E6352) use an > indirect access through two SMI Command and Data registers. > > Other models (e.g. 88E6060) using less than 16 internal SMI addresses > always use a direct access. > > Add a capability flag to describe chips supporting the (indirect) > Multi-chip Addressing Mode, and a low-level API to access the registers > via SMI. > > Other accesses (like Ethernet management frames) may be added later. > > Signed-off-by: Vivien Didelot Reviewed-by: Andrew Lunn This series is now ready for merging. Thanks Andrew