From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752585AbcF1Jte (ORCPT ); Tue, 28 Jun 2016 05:49:34 -0400 Received: from pandora.armlinux.org.uk ([78.32.30.218]:58150 "EHLO pandora.armlinux.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752344AbcF1Jtc (ORCPT ); Tue, 28 Jun 2016 05:49:32 -0400 Date: Tue, 28 Jun 2016 10:49:14 +0100 From: Russell King - ARM Linux To: patrice.chotard@st.com Cc: linux-arm-kernel@lists.infradead.org, kernel@stlinux.com, linux-kernel@vger.kernel.org, peter.griffin@linaro.org, lee.jones@linaro.org Subject: Re: [PATCH] ARM: sti: Implement dummy L2 cache's write_sec Message-ID: <20160628094914.GI1041@n2100.armlinux.org.uk> References: <1467106837-20996-1-git-send-email-patrice.chotard@st.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1467106837-20996-1-git-send-email-patrice.chotard@st.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jun 28, 2016 at 11:40:37AM +0200, patrice.chotard@st.com wrote: > From: Patrice Chotard > > This patch implements the write_sec callback that handle PL310 > secure registers writes. > This callback is just a stub for now, to avoid system crash. > Later, it could handle SMC calls so that TZ handles the needed writes. Is there much point having the L2 cache DT node enabled if you have no support for the writes, which are required for the hardware to be enabled? -- RMK's Patch system: http://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net.