From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752570AbcGAC4l (ORCPT ); Thu, 30 Jun 2016 22:56:41 -0400 Received: from mail-qk0-f193.google.com ([209.85.220.193]:32886 "EHLO mail-qk0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751953AbcGAC4f (ORCPT ); Thu, 30 Jun 2016 22:56:35 -0400 Date: Thu, 30 Jun 2016 21:38:25 -0500 From: Rob Herring To: William Wu Cc: gregkh@linuxfoundation.org, balbi@kernel.org, heiko@sntech.de, linux-rockchip@lists.infradead.org, briannorris@google.com, dianders@google.com, kever.yang@rock-chips.com, huangtao@rock-chips.com, frank.wang@rock-chips.com, eddie.cai@rock-chips.com, John.Youn@synopsys.com, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, sergei.shtylyov@cogentembedded.com, mark.rutland@arm.com, devicetree@vger.kernel.org Subject: Re: [PATCH v5 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk Message-ID: <20160701023825.GA27978@rob-hp-laptop> References: <1467285176-25222-1-git-send-email-william.wu@rock-chips.com> <1467285176-25222-5-git-send-email-william.wu@rock-chips.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1467285176-25222-5-git-send-email-william.wu@rock-chips.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jun 30, 2016 at 07:12:55PM +0800, William Wu wrote: > Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, > which specifies whether disable delay PHY power change > from P0 to P1/P2/P3 when link state changing from U0 > to U1/U2/U3 respectively. > > Signed-off-by: William Wu > --- > Changes in v5: > - None > > Changes in v4: > - rebase on top of balbi testing/next, remove pdata (balbi) > > Changes in v3: > - None > > Changes in v2: > - None > > Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++ > drivers/usb/dwc3/core.c | 5 +++++ > drivers/usb/dwc3/core.h | 3 +++ > 3 files changed, 10 insertions(+) > > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt > index 34d13a5..bd5bef0 100644 > --- a/Documentation/devicetree/bindings/usb/dwc3.txt > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt > @@ -42,6 +42,8 @@ Optional properties: > - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists > in GUSB2PHYCFG, specify that USB2 PHY doesn't provide > a free-running PHY clock. > + - snps,dis_del_phy_power_chg_quirk: when set core will change PHY power > + from P0 to P1/P2/P3 without delay. Use '-', not '_'. > - snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface. > - snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY > with an 8- or 16-bit interface. Value 0 select 8-bit