From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756450AbcGHWZY (ORCPT ); Fri, 8 Jul 2016 18:25:24 -0400 Received: from bombadil.infradead.org ([198.137.202.9]:58387 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756283AbcGHWZR (ORCPT ); Fri, 8 Jul 2016 18:25:17 -0400 Date: Sat, 9 Jul 2016 00:25:09 +0200 From: Peter Zijlstra To: Jiri Olsa Cc: mingo@kernel.org, acme@kernel.org, linux-kernel@vger.kernel.org, andi@firstfloor.org, eranian@google.com, jolsa@kernel.org, torvalds@linux-foundation.org, davidcc@google.com, alexander.shishkin@linux.intel.com, namhyung@kernel.org, kan.liang@intel.com, khandual@linux.vnet.ibm.com Subject: Re: [RFC][PATCH 1/7] perf/x86/intel: Rework the large PEBS setup code Message-ID: <20160708222509.GL30927@twins.programming.kicks-ass.net> References: <20160708133059.031522978@infradead.org> <20160708134113.290879090@infradead.org> <20160708163616.GA2392@krava> <20160708220047.GK30909@twins.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20160708220047.GK30909@twins.programming.kicks-ass.net> User-Agent: Mutt/1.5.23.1 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Jul 09, 2016 at 12:00:47AM +0200, Peter Zijlstra wrote: > Yes, you're right. Let me try and see if I can make that better. Something like so? --- --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -831,6 +831,18 @@ static inline void pebs_update_threshold ds->pebs_interrupt_threshold = threshold; } +static void pebs_update_state(bool needs_cb, struct cpu_hw_events *cpuc, struct pmu *pmu) +{ + if (needs_cb != pebs_needs_sched_cb(cpuc)) { + if (!needs_cb) + perf_sched_cb_inc(pmu); + else + perf_sched_cb_dec(pmu); + + pebs_update_threshold(cpuc); + } +} + static void intel_pmu_pebs_add(struct perf_event *event) { struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); @@ -841,10 +853,7 @@ static void intel_pmu_pebs_add(struct pe if (hwc->flags & PERF_X86_EVENT_FREERUNNING) cpuc->n_large_pebs++; - if (!needs_cb && pebs_needs_sched_cb(cpuc)) - perf_sched_cb_inc(event->ctx->pmu); - - pebs_update_threshold(cpuc); + pebs_update_state(needs_cb, cpuc, event->ctx->pmu); } void intel_pmu_pebs_enable(struct perf_event *event) @@ -884,11 +893,7 @@ static void intel_pmu_pebs_del(struct pe if (hwc->flags & PERF_X86_EVENT_FREERUNNING) cpuc->n_large_pebs--; - if (needs_cb && !pebs_needs_sched_cb(cpuc)) - perf_sched_cb_dec(event->ctx->pmu); - - if (cpuc->n_pebs) - pebs_update_threshold(cpuc); + pebs_update_state(needs_cb, cpuc, event->ctx->pmu); } void intel_pmu_pebs_disable(struct perf_event *event)