From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752741AbcGTCmX (ORCPT ); Tue, 19 Jul 2016 22:42:23 -0400 Received: from shards.monkeyblade.net ([184.105.139.130]:42050 "EHLO shards.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752416AbcGTCmV (ORCPT ); Tue, 19 Jul 2016 22:42:21 -0400 Date: Tue, 19 Jul 2016 19:42:20 -0700 (PDT) Message-Id: <20160719.194220.1605569742108600970.davem@davemloft.net> To: vivien.didelot@savoirfairelinux.com Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@savoirfairelinux.com, andrew@lunn.ch, f.fainelli@gmail.com Subject: Re: [PATCH net-next v3 00/12] net: dsa: mv88e6xxx: Global2 cleanup and STP From: David Miller In-Reply-To: <20160719004540.1066-1-vivien.didelot@savoirfairelinux.com> References: <20160719004540.1066-1-vivien.didelot@savoirfairelinux.com> X-Mailer: Mew version 6.7 on Emacs 24.5 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.5.12 (shards.monkeyblade.net [149.20.54.216]); Tue, 19 Jul 2016 19:42:20 -0700 (PDT) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Vivien Didelot Date: Mon, 18 Jul 2016 20:45:28 -0400 > The Marvell switches registers are organized in distinct internal SMI > devices, such as PHY, Port, Global 1 or Global 2 registers sets. > > Since not all chips support every registers sets or have slightly > differences in them (such as old 88E6060 or new 88E6390 likely to be > supported soon), make the setup code clearer now by removing a few > family checks and adding flags to describe the Global 2 registers map. > > This patchset enables basic STP support and bridging on most chips when > getting rid of a few inconsistencies in chip descriptions (patch 1) and > add bridge Ageing Time support to DSA and the mv88e6xxx driver. Series applied.