From: Marcelo Tosatti <mtosatti@redhat.com>
To: "Luck, Tony" <tony.luck@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>,
Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@elte.hu>,
"H. Peter Anvin" <h.peter.anvin@intel.com>,
Tejun Heo <tj@kernel.org>, Borislav Petkov <bp@suse.de>,
Stephane Eranian <eranian@google.com>,
Peter Zijlstra <peterz@infradead.org>,
David Carrillo-Cisneros <davidcc@google.com>,
Ravi V Shankar <ravi.v.shankar@intel.com>,
Vikas Shivappa <vikas.shivappa@linux.intel.com>,
Sai Prakhya <sai.praneeth.prakhya@intel.com>,
linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>
Subject: Re: [PATCH 04/32] x86/intel_rdt: Add L3 cache capacity bitmask management
Date: Sat, 23 Jul 2016 01:31:03 -0300 [thread overview]
Message-ID: <20160723043103.GA22015@amt.cnet> (raw)
In-Reply-To: <20160722214322.GA938@intel.com>
On Fri, Jul 22, 2016 at 02:43:23PM -0700, Luck, Tony wrote:
> On Fri, Jul 22, 2016 at 04:12:04AM -0300, Marcelo Tosatti wrote:
> > How does this patchset handle the following condition:
> >
> > 6) Create reservations in such a way that the sum is larger than
> > total amount of cache, and CPU pinning (example from Karen Noel):
> >
> > VM-1 on socket-1 with 80% of reservation.
> > VM-2 on socket-2 with 80% of reservation.
> > VM-1 pinned to socket-1.
> > VM-2 pinned to socket-2.
>
> That's legal, but perhaps we need a description of
> overlapping cache reservations.
>
> Hardware tells you how finely you can divide the cache (and this
> information is shown in /sys/fs/resctrl/info/l3/max_cbm_len to save
> you from digging in CPUID leaves). E.g. on Broadwell the value is
> 20, so you can control cache allocations in 5% slices.
>
> A bitmask defines which slices you can use (and h/w has the restriction
> that you must have contiguous '1' bits in any mask). So you can pick
> your 80% using 0x0ffff, 0x1fffe, 0x3fffc, 0x7fff8 or 0xffff0.
>
> There is no requirement that masks be exclusive of each other. So
> you might pick the two extremes: 0x0ffff and 0xffff0 for your two
> VM's in this example. Each would be allowed to allocate up to 80%,
> but with a big overlap in the middle. Each has 20% exclusive, but
> there is a 60% range in the middle that they would compete for.
This are different sockets, so there is no competing/sharing of L3 cache
here: the question is about whether the interface allows the
user to specify that 80/80 reservation without complaining:
because the VM's are pinned, they will never actually
share the same L3 cache.
(haven't finished reading the patchset to be certain).
> Is this specific case useful? Possibly not. I think the more common
> overlap cases might be between processes that you know have shared
> code/data. Also the case where some rdtgroup has access to allocate
> in the entire cache (mask 0xfffff on Broadwell) and some other
> rdtgroups
> have limited cache allocation with less bits in the mask.
>
> -Tony
All you have to do is to build the bitmask for a given processor
from the union of the tasks which have been scheduled on that
processor.
next prev parent reply other threads:[~2016-07-26 2:13 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-13 1:02 [PATCH 00/32] Enable Intel Resource Allocation in Resource Director Technology Fenghua Yu
2016-07-13 1:02 ` [PATCH 01/32] x86/intel_rdt: Cache Allocation documentation Fenghua Yu
2016-07-13 1:02 ` [PATCH 02/32] x86/intel_rdt: Add support for Cache Allocation detection Fenghua Yu
2016-07-26 19:00 ` Nilay Vaish
2016-07-13 1:02 ` [PATCH 03/32] x86/intel_rdt: Add Class of service management Fenghua Yu
2016-07-13 1:02 ` [PATCH 04/32] x86/intel_rdt: Add L3 cache capacity bitmask management Fenghua Yu
2016-07-22 7:12 ` Marcelo Tosatti
2016-07-22 21:43 ` Luck, Tony
2016-07-23 4:31 ` Marcelo Tosatti [this message]
2016-07-26 3:18 ` Luck, Tony
2016-07-26 17:10 ` Shivappa Vikas
2016-07-13 1:02 ` [PATCH 05/32] x86/intel_rdt: Implement scheduling support for Intel RDT Fenghua Yu
2016-07-25 16:25 ` Nilay Vaish
2016-07-25 16:31 ` Nilay Vaish
2016-07-25 18:05 ` Luck, Tony
2016-07-25 22:47 ` David Carrillo-Cisneros
2016-07-13 1:02 ` [PATCH 06/32] x86/intel_rdt: Hot cpu support for Cache Allocation Fenghua Yu
2016-07-13 9:19 ` Thomas Gleixner
2016-07-21 19:46 ` Shivappa Vikas
2016-07-14 0:40 ` David Carrillo-Cisneros
2016-07-14 22:58 ` Yu, Fenghua
2016-07-13 1:02 ` [PATCH 07/32] x86/intel_rdt: Intel haswell Cache Allocation enumeration Fenghua Yu
2016-07-13 1:02 ` [PATCH 08/32] Define CONFIG_INTEL_RDT Fenghua Yu
2016-07-13 10:25 ` Thomas Gleixner
2016-07-13 18:05 ` Yu, Fenghua
2016-07-13 21:09 ` Thomas Gleixner
2016-07-13 21:18 ` Yu, Fenghua
2016-07-13 1:02 ` [PATCH 09/32] x86/intel_rdt: Intel Code Data Prioritization detection Fenghua Yu
2016-07-13 1:02 ` [PATCH 10/32] x86/intel_rdt: Adds support to enable Code Data Prioritization Fenghua Yu
2016-07-26 19:23 ` Nilay Vaish
2016-07-26 20:32 ` Shivappa Vikas
2016-07-13 1:02 ` [PATCH 11/32] x86/intel_rdt: Class of service and capacity bitmask management for CDP Fenghua Yu
2016-07-13 1:02 ` [PATCH 12/32] x86/intel_rdt: Hot cpu update for code data prioritization Fenghua Yu
2016-07-13 1:02 ` [PATCH 13/32] Documentation, x86: Documentation for Intel resource allocation user interface Fenghua Yu
2016-07-13 12:47 ` Thomas Gleixner
2016-07-13 17:13 ` Luck, Tony
2016-07-14 6:53 ` Thomas Gleixner
2016-07-14 17:16 ` Luck, Tony
2016-07-19 12:32 ` Thomas Gleixner
2016-08-04 23:38 ` Yu, Fenghua
2016-07-27 16:20 ` Nilay Vaish
2016-07-27 16:57 ` Luck, Tony
2016-08-03 22:15 ` Marcelo Tosatti
2016-07-13 1:02 ` [PATCH 14/32] x86/cpufeatures: Get max closid and max cbm len and clean feature comments and code Fenghua Yu
2016-07-27 16:49 ` Nilay Vaish
2016-07-13 1:02 ` [PATCH 15/32] cacheinfo: Introduce cache id Fenghua Yu
2016-07-27 17:04 ` Nilay Vaish
2016-07-13 1:02 ` [PATCH 16/32] Documentation, ABI: Add a document entry for " Fenghua Yu
2016-07-13 1:02 ` [PATCH 17/32] x86, intel_cacheinfo: Enable cache id in x86 Fenghua Yu
2016-07-28 5:41 ` Nilay Vaish
2016-07-13 1:02 ` [PATCH 18/32] drivers/base/cacheinfo.c: Export some cacheinfo functions for others to use Fenghua Yu
2016-07-13 1:02 ` [PATCH 19/32] sched.h: Add rg_list and rdtgroup in task_struct Fenghua Yu
2016-07-13 12:56 ` Thomas Gleixner
2016-07-13 17:50 ` Yu, Fenghua
2016-07-28 5:53 ` Nilay Vaish
2016-07-13 1:02 ` [PATCH 20/32] magic number for rscctrl file system Fenghua Yu
2016-07-28 5:57 ` Nilay Vaish
2016-07-13 1:02 ` [PATCH 21/32] x86/intel_rdt.h: Header for inter_rdt.c Fenghua Yu
2016-07-28 14:07 ` Nilay Vaish
2016-07-13 1:02 ` [PATCH 22/32] x86/intel_rdt_rdtgroup.h: Header for user interface Fenghua Yu
2016-07-13 1:02 ` [PATCH 23/32] x86/intel_rdt.c: Extend RDT to per cache and per resources Fenghua Yu
2016-07-13 13:07 ` Thomas Gleixner
2016-07-13 17:40 ` Yu, Fenghua
2016-07-13 1:02 ` [PATCH 24/32] Task fork and exit for rdtgroup Fenghua Yu
2016-07-13 13:14 ` Thomas Gleixner
2016-07-13 17:32 ` Yu, Fenghua
2016-07-13 21:02 ` Thomas Gleixner
2016-07-13 21:22 ` Yu, Fenghua
2016-07-13 1:02 ` [PATCH 25/32] x86/intel_rdt_rdtgroup.c: User interface for RDT Fenghua Yu
2016-07-14 12:30 ` Thomas Gleixner
2016-07-13 1:02 ` [PATCH 26/32] x86/intel_rdt_rdtgroup.c: Create info directory Fenghua Yu
2016-07-13 1:03 ` [PATCH 27/32] x86/intel_rdt_rdtgroup.c: Implement rscctrl file system commands Fenghua Yu
2016-07-13 1:03 ` [PATCH 28/32] x86/intel_rdt_rdtgroup.c: Read and write cpus Fenghua Yu
2016-07-13 1:03 ` [PATCH 29/32] x86/intel_rdt_rdtgroup.c: Tasks iterator and write Fenghua Yu
2016-07-13 1:03 ` [PATCH 30/32] x86/intel_rdt_rdtgroup.c: Process schemas input from rscctrl interface Fenghua Yu
2016-07-14 0:41 ` David Carrillo-Cisneros
2016-07-14 6:11 ` Thomas Gleixner
2016-07-14 6:16 ` Yu, Fenghua
2016-07-14 6:32 ` Yu, Fenghua
2016-07-13 1:03 ` [PATCH 31/32] MAINTAINERS: Add maintainer for Intel RDT resource allocation Fenghua Yu
2016-07-13 1:03 ` [PATCH 32/32] x86/Makefile: Build intel_rdt_rdtgroup.c Fenghua Yu
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