From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757012AbcG1TMJ (ORCPT ); Thu, 28 Jul 2016 15:12:09 -0400 Received: from mezzanine.sirena.org.uk ([106.187.55.193]:45844 "EHLO mezzanine.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753876AbcG1TMF (ORCPT ); Thu, 28 Jul 2016 15:12:05 -0400 Date: Thu, 28 Jul 2016 20:11:53 +0100 From: Mark Brown To: Rich Felker Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-sh@vger.kernel.org, Rob Herring , Mark Rutland Message-ID: <20160728191153.GL11806@sirena.org.uk> References: <2a46090a5a7c177b7eca83f68406650844423e7f.1469686300.git.dalias@libc.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="Epi5nlKhkk4Kf+ga" Content-Disposition: inline In-Reply-To: <2a46090a5a7c177b7eca83f68406650844423e7f.1469686300.git.dalias@libc.org> X-Cookie: Are you still an ALCOHOLIC? User-Agent: Mutt/1.6.0 (2016-04-01) X-SA-Exim-Connect-IP: 2a01:348:6:8808:fab::3 X-SA-Exim-Mail-From: broonie@sirena.org.uk Subject: Re: [PATCH v4 2/2] spi: add driver for J-Core SPI controller X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: No (on mezzanine.sirena.org.uk); Unknown failure Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --Epi5nlKhkk4Kf+ga Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Sun, Apr 03, 2016 at 05:12:45AM +0000, Rich Felker wrote: > +config SPI_JCORE > + tristate "J-Core SPI Master" > + depends on OF > + An architecture or SoC dependency with || COMPILE_TEST would be useful for avoiding cluttering Kconfig for other users. Though as this is in a FPGA it's perhaps likely people will pick this up for other FPGAs so perhaps a comment to that effect if it seems likely. > +static void jcore_spi_baudrate(struct jcore_spi *hw, int speed) > +{ > + if (speed == hw->speed_hz) return; > + hw->speed_hz = speed; > + if (speed >= hw->clock_freq/2) Coding style, spaces around /. > + return count + /* The SPI clock rate controlled via a configurable clock divider > + * which is applied to the reference clock. A 50 MHz reference is > + * most suitable for obtaining standard SPI clock rates, but some > + * designs may have a different reference clock, and the DT must > + * make the driver aware so that it can properly program the > + * requested rate. If omitted, 50 MHz is assumed. */ > + clock_freq = 50000000; > + of_property_read_u32(node, "clock-frequency", &clock_freq); > + hw->clock_freq = clock_freq; Why are you not using the clock API for this? Just require a clock and use clk_get_rate() to find out what rate it is. > + pdev->dev.dma_mask = 0; Why are we doing this? There's no DMA code... > + dev_info(&pdev->dev, "base %p, noirq\n", hw->base); This is just adding noise to the boot, just remove it - it's useful to log information we get from the silicon but things like the base address don't really add anything and end up cluttering (and slowing) the boot when everything does it. --Epi5nlKhkk4Kf+ga Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAEBCAAGBQJXmlj4AAoJECTWi3JdVIfQy5QH/35g8/6zlsdIcQujUaCJiXiO 2zojNTrkofTDrfsHQCT7/5Pp82Q9Dze1XZ3LmAEFLg/mWgJX5VZA89WYBEAw/Jkf dEpLBN/FfnnLJH60ReZf80nytfbKIidLm8gpfjrGZ+KNM1UTACOrN5kkwvdJHk+t 7jQZJ5M/rOu++CFKBmMIE3zXk81GkbPe1OBs8/S0/phTUFEah7GxaJ8i6iK5cECM du+mzvYU2D9oiPC4rFeQw3Tcigmm4GmYItsqq3ePYxJBuEB0nHrU3+xFbFvw1OgR rMfZjDHM0KWFdZaxozl4UxqbC0RWE8+cbzmjhglxe54BjvDjh59wzhRhfH/uXYk= =1y9J -----END PGP SIGNATURE----- --Epi5nlKhkk4Kf+ga--