From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932764AbcHKQmP (ORCPT ); Thu, 11 Aug 2016 12:42:15 -0400 Received: from mail.skyhub.de ([78.46.96.112]:35344 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932550AbcHKQmN (ORCPT ); Thu, 11 Aug 2016 12:42:13 -0400 Date: Thu, 11 Aug 2016 18:41:50 +0200 From: Borislav Petkov To: Matt Fleming Cc: Peter Zijlstra , linux-kernel@vger.kernel.org, Ingo Molnar Subject: Re: [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2 Message-ID: <20160811164150.GB7296@nazgul.tnic> References: <1470928902-31196-1-git-send-email-matt@codeblueprint.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1470928902-31196-1-git-send-email-matt@codeblueprint.co.uk> User-Agent: Mutt/1.6.0 (2016-04-01) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Drop stable from CC. On Thu, Aug 11, 2016 at 04:21:42PM +0100, Matt Fleming wrote: > While the Intel PMU monitors the LLC when perf enables the > HW_CACHE_REFERENCES and HW_CACHE_MISSES events, these events monitor > L1 instruction cache fetches (0x0080) and instruction cache misses > (0x0081) on the AMD PMU. > > This is extremely confusing when monitoring the same workload across > Intel and AMD machines, since parameters like, > > $ perf stat -e cache-references,cache-misses > > measure completely different things. > > Instead, make the AMD PMU measure instruction/data cache fill requests > to the L2 and instruction/data cache misses in the L2 when > HW_CACHE_REFERENCES and HW_CACHE_MISSES are enabled, respectively. > That way the events measure unified caches on both platforms. I guess that's closer. Even though LLC is not always L2 on AMD (some have L3). Btw, what are the exact events for PERF_COUNT_HW_CACHE_REFERENCES and PERF_COUNT_HW_CACHE_MISSES called on Intel? I could try to find better/more fitting event selectors on AMD... > Signed-off-by: Matt Fleming > Cc: Peter Zijlstra > Cc: Ingo Molnar > Cc: Borislav Petkov > Cc: > --- > arch/x86/events/amd/core.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c > index e07a22bb9308..8fd8bf79f32b 100644 > --- a/arch/x86/events/amd/core.c > +++ b/arch/x86/events/amd/core.c > @@ -119,8 +119,8 @@ static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] = > { > [PERF_COUNT_HW_CPU_CYCLES] = 0x0076, > [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, > - [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0080, > - [PERF_COUNT_HW_CACHE_MISSES] = 0x0081, > + [PERF_COUNT_HW_CACHE_REFERENCES] = 0x037d, > + [PERF_COUNT_HW_CACHE_MISSES] = 0x037e, > [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2, > [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3, > [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00d0, /* "Decoder empty" event */ Btw, there's also amd_event_mapping in arch/x86/kvm/pmu_amd.c which has duplicated amd_perfmon_event_map. Would need adjusting too. -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply. --