From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752672AbcHLX6F (ORCPT ); Fri, 12 Aug 2016 19:58:05 -0400 Received: from shards.monkeyblade.net ([184.105.139.130]:56155 "EHLO shards.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751966AbcHLX6D (ORCPT ); Fri, 12 Aug 2016 19:58:03 -0400 Date: Fri, 12 Aug 2016 16:57:53 -0700 (PDT) Message-Id: <20160812.165753.1652467337612232120.davem@davemloft.net> To: appana.durga.rao@xilinx.com Cc: robh+dt@kernel.org, mark.rutland@arm.com, michal.simek@xilinx.com, soren.brinkmann@xilinx.com, appanad@xilinx.com, f.fainelli@gmail.com, andrew@lunn.ch, punnaia@xilinx.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: Re: [PATCH v6 0/3] net: phy: Add xilinx gmiitorgmii converter support From: David Miller In-Reply-To: <1470808208-32133-1-git-send-email-appanad@xilinx.com> References: <1470808208-32133-1-git-send-email-appanad@xilinx.com> X-Mailer: Mew version 6.7 on Emacs 24.5 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.5.12 (shards.monkeyblade.net [149.20.54.216]); Fri, 12 Aug 2016 16:57:56 -0700 (PDT) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kedareswara rao Appana Date: Wed, 10 Aug 2016 11:20:05 +0530 > The Gigabit Media Independent Interface (GMII) to Reduced Gigabit Media > Independent Interface (RGMII) core provides the RGMII between RGMII-compliant > Ethernet physical media devices (PHY) and the Gigabit Ethernet controller. > This core can be used in all three modes of operation(10/100/1000 Mb/s). > The Management Data Input/Output (MDIO) interface is used to configure the > Speed of operation. This core can switch dynamically between the three > Different speed modes by configuring the conveter register through mdio write. > > The conveter sits b/w the MAC and external phy like below > > MACB <==> GMII2RGMII <==> RGMII_PHY > > MDIO <========> GMII2RGMII > MCAB <=======> > <========> RGMII > > Using MAC MDIO bus we can access both the converter and the external PHY. > We need to program the line speed of the converter during run time based > On the external phy negotiated speed. > > This patch series does the below > ---> Add mask for Control register 10Mbps speed. > ---> Add support for xilinx gmiitorgmii converter. Series applied, thanks.