From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932349AbcHSNea (ORCPT ); Fri, 19 Aug 2016 09:34:30 -0400 Received: from bombadil.infradead.org ([198.137.202.9]:46761 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932203AbcHSNe1 (ORCPT ); Fri, 19 Aug 2016 09:34:27 -0400 Date: Fri, 19 Aug 2016 15:34:22 +0200 From: Peter Zijlstra To: Borislav Petkov Cc: Matt Fleming , linux-kernel@vger.kernel.org, Ingo Molnar Subject: Re: [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2 Message-ID: <20160819133422.GI10121@twins.programming.kicks-ass.net> References: <1470928902-31196-1-git-send-email-matt@codeblueprint.co.uk> <20160811164150.GB7296@nazgul.tnic> <20160815151316.GI30909@codeblueprint.co.uk> <20160818162522.GB5049@nazgul.tnic> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20160818162522.GB5049@nazgul.tnic> User-Agent: Mutt/1.5.23.1 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Aug 18, 2016 at 06:25:22PM +0200, Borislav Petkov wrote: > > > I could try to find better/more fitting event selectors on AMD... > > > > If you've got any other suggestions, I'm all ears. > > So there are no LLC events on AMD in the sense that there are no > event selectors which always mean last-level cache and select those > automagically, no matter whether the LLC is the L2, L3 and so on, > depending on the part. > > If we have to be correct on AMD, we'd have to check whether the part has > an L3 and then choose the L3 events, say, something like > > "EventSelect 4E1h L3 Cache Misses" and "EventSelect 4E2h L3 Fills caused > by L2 Evictions" Can't those events are NB events and cannot be used on per CPU counters. The 7D,7E L2 events are the best that are available on AMD afaict.