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Date: Mon, 29 Aug 2016 16:14:37 +0200
From: Peter Zijlstra <peterz@infradead.org>
To: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: vince@deater.net, Ingo Molnar <mingo@redhat.com>,
        linux-kernel@vger.kernel.org, eranian@google.com,
        Arnaldo Carvalho de Melo <acme@infradead.org>
Subject: Re: [PATCH 1/3] perf/x86/intel/bts: Fix confused ordering of PMU
 callbacks
Message-ID: <20160829141437.GU10153@twins.programming.kicks-ass.net>
References: <1471942474-1854-1-git-send-email-alexander.shishkin@linux.intel.com>
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On Wed, Aug 24, 2016 at 05:15:54PM +0300, Alexander Shishkin wrote:
> @@ -221,10 +245,13 @@ static void __bts_event_start(struct perf_event *event)
>  
>  	/*
>  	 * local barrier to make sure that ds configuration made it
> -	 * before we enable BTS
> +	 * before we enable BTS and bts::state goes ACTIVE
>  	 */
>  	wmb();
>  
> +	/* INACTIVE/STOPPED -> ACTIVE */
> +	WRITE_ONCE(bts->state, BTS_STATE_ACTIVE);
> +
>  	intel_pmu_enable_bts(config);
>  
>  }

Alexander, were you going to post a new version of this patch without
the barrier confusion?