From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758713AbcH3Rd7 (ORCPT ); Tue, 30 Aug 2016 13:33:59 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:62509 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758618AbcH3Rd4 (ORCPT ); Tue, 30 Aug 2016 13:33:56 -0400 From: Paul Burton To: , Ralf Baechle CC: Paul Burton , Marc Zyngier , Jason Cooper , Thomas Gleixner , Subject: [PATCH v2 15/26] irqchip: mips-cpu: Replace magic 0x100 with IE_SW0 Date: Tue, 30 Aug 2016 18:29:18 +0100 Message-ID: <20160830172929.16948-16-paul.burton@imgtec.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20160830172929.16948-1-paul.burton@imgtec.com> References: <20160830172929.16948-1-paul.burton@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.100.200.118] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Replace use of the magic number 0x100 (ie. bit 8) with the more explanatory IE_SW0 (ie. interrupt enable for software interrupt 0) or C_SW0 (ie. cause bit for software interrupt 0) as appropriate. Signed-off-by: Paul Burton --- Changes in v2: None drivers/irqchip/irq-mips-cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c index 8c504f5..e6b4136 100644 --- a/drivers/irqchip/irq-mips-cpu.c +++ b/drivers/irqchip/irq-mips-cpu.c @@ -41,13 +41,13 @@ static inline void unmask_mips_irq(struct irq_data *d) { - set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); + set_c0_status(IE_SW0 << (d->irq - MIPS_CPU_IRQ_BASE)); irq_enable_hazard(); } static inline void mask_mips_irq(struct irq_data *d) { - clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); + clear_c0_status(IE_SW0 << (d->irq - MIPS_CPU_IRQ_BASE)); irq_disable_hazard(); } @@ -70,7 +70,7 @@ static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d) { unsigned int vpflags = dvpe(); - clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); + clear_c0_cause(C_SW0 << (d->irq - MIPS_CPU_IRQ_BASE)); evpe(vpflags); unmask_mips_irq(d); return 0; @@ -83,7 +83,7 @@ static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d) static void mips_mt_cpu_irq_ack(struct irq_data *d) { unsigned int vpflags = dvpe(); - clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); + clear_c0_cause(C_SW0 << (d->irq - MIPS_CPU_IRQ_BASE)); evpe(vpflags); mask_mips_irq(d); } -- 2.9.3