From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753308AbcIBVkk (ORCPT ); Fri, 2 Sep 2016 17:40:40 -0400 Received: from bh-25.webhostbox.net ([208.91.199.152]:38986 "EHLO bh-25.webhostbox.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751680AbcIBVki (ORCPT ); Fri, 2 Sep 2016 17:40:38 -0400 Date: Fri, 2 Sep 2016 14:40:34 -0700 From: Guenter Roeck To: Bjorn Helgaas Cc: Shawn Lin , devicetree@vger.kernel.org, Wenrui Li , Heiko Stuebner , Arnd Bergmann , Marc Zyngier , linux-pci@vger.kernel.org, Brian Norris , linux-kernel@vger.kernel.org, Doug Anderson , linux-rockchip@lists.infradead.org, Rob Herring Subject: Re: [PATCH v2 10/15] Group related CSR definitions together. Message-ID: <20160902214034.GB31011@roeck-us.net> References: <20160902154501.8650.99790.stgit@bhelgaas-glaptop2.roam.corp.google.com> <20160902155518.8650.89467.stgit@bhelgaas-glaptop2.roam.corp.google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20160902155518.8650.89467.stgit@bhelgaas-glaptop2.roam.corp.google.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-Authenticated_sender: guenter@roeck-us.net X-OutGoing-Spam-Status: No, score=-1.0 X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - bh-25.webhostbox.net X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - roeck-us.net X-Get-Message-Sender-Via: bh-25.webhostbox.net: authenticated_id: guenter@roeck-us.net X-Authenticated-Sender: bh-25.webhostbox.net: guenter@roeck-us.net X-Source: X-Source-Args: X-Source-Dir: Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Sep 02, 2016 at 10:55:19AM -0500, Bjorn Helgaas wrote: > > --- > drivers/pci/host/pcie-rockchip.c | 148 +++++++++++++++++++------------------- > 1 file changed, 74 insertions(+), 74 deletions(-) > > diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c > index 6edfce5..fe1b52f 100644 > --- a/drivers/pci/host/pcie-rockchip.c > +++ b/drivers/pci/host/pcie-rockchip.c > @@ -37,21 +37,27 @@ > #include > #include > > -#define PCIE_CLIENT_BASE 0x0 > -#define PCIE_RC_CONFIG_BASE 0xa00000 > -#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c) > -#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0x0d0) > -#define PCIE_RC_CONFIG_LCS_RETRAIN_LINK BIT(5) > -#define PCIE_RC_CONFIG_LCS_LBMIE BIT(10) > -#define PCIE_RC_CONFIG_LCS_LABIE BIT(11) > -#define PCIE_RC_CONFIG_LCS_LBMS BIT(30) > -#define PCIE_RC_CONFIG_LCS_LAMS BIT(31) > -#define PCIE_CORE_CTRL_MGMT_BASE 0x900000 > -#define PCIE_CORE_AXI_CONF_BASE 0xc00000 > -#define PCIE_CORE_AXI_INBOUND_BASE 0xc00800 > -#define PCIE_CLIENT_BASIC_STATUS1 (PCIE_CLIENT_BASE + 0x48) > -#define PCIE_CLIENT_INT_MASK (PCIE_CLIENT_BASE + 0x4c) > -#define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50) > +/* > + * The upper 16 bits of PCIE_CLIENT_BASE are a write mask for the lower 16 > + * bits. This allows atomic updates of the register without locking. > + */ > +#define HIWORD_UPDATE(mask, val) ((mask << 16) | val) > + (mask), (val) > +#define ENCODE_LANES(x) (((x >> 1) & 3) << 4) (x) Guenter