From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757322AbcIOXeR (ORCPT ); Thu, 15 Sep 2016 19:34:17 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:35935 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757149AbcIOXeC (ORCPT ); Thu, 15 Sep 2016 19:34:02 -0400 From: Kyle Huey X-Google-Original-From: Kyle Huey To: "Robert O'Callahan" Cc: linux-kernel@vger.kernel.org, Dave Hansen , Andy Lutomirski , Dmitry Safonov <0x7f454c46@gmail.com>, Borislav Petkov , linux-api@vger.kernel.org, xen-devel@lists.xenproject.org, Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), Andy Lutomirski , Peter Zijlstra , Huang Rui , Boris Ostrovsky , "Rafael J. Wysocki" , Len Brown , Srinivas Pandruvada , Alexander Shishkin , Aravind Gopalakrishnan , Vladimir Zapolskiy , Kristen Carlson Accardi Subject: [PATCH v3 2/3] x86 Test and expose CPUID faulting capabilities in /proc/cpuinfo Date: Thu, 15 Sep 2016 16:33:23 -0700 Message-Id: <20160915233324.6060-3-khuey@kylehuey.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20160915233324.6060-1-khuey@kylehuey.com> References: <20160915233324.6060-1-khuey@kylehuey.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Signed-off-by: Kyle Huey --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/cpu/scattered.c | 14 ++++++++++++++ 3 files changed, 16 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 92a8308..78b9d06 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -190,6 +190,7 @@ #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ +#define X86_FEATURE_CPUID_FAULT ( 7*32+ 4) /* Intel CPUID faulting */ #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 56f4c66..83908d5 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -41,6 +41,7 @@ #define MSR_IA32_PERFCTR1 0x000000c2 #define MSR_FSB_FREQ 0x000000cd #define MSR_PLATFORM_INFO 0x000000ce +#define CPUID_FAULTING_SUPPORT (1UL << 31) #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 #define NHM_C3_AUTO_DEMOTE (1UL << 25) diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index 8cb57df..d502da1 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -24,6 +24,17 @@ enum cpuid_regs { CR_EBX }; +static int supports_cpuid_faulting(void) +{ + unsigned int lo, hi; + + if (rdmsr_safe(MSR_PLATFORM_INFO, &lo, &hi) == 0 && + (lo & CPUID_FAULTING_SUPPORT)) + return 1; + else + return 0; +} + void init_scattered_cpuid_features(struct cpuinfo_x86 *c) { u32 max_level; @@ -54,4 +65,7 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c) if (regs[cb->reg] & (1 << cb->bit)) set_cpu_cap(c, cb->feature); } + + if (supports_cpuid_faulting()) + set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); } -- 2.9.3