From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936175AbcI3FyV (ORCPT ); Fri, 30 Sep 2016 01:54:21 -0400 Received: from mail-pa0-f65.google.com ([209.85.220.65]:33979 "EHLO mail-pa0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935705AbcI3FyM (ORCPT ); Fri, 30 Sep 2016 01:54:12 -0400 Date: Fri, 30 Sep 2016 13:53:52 +0800 From: Boqun Feng To: "Paul E. McKenney" Cc: Will Deacon , Peter Zijlstra , linux-kernel@vger.kernel.org, mingo@kernel.org, dhowells@redhat.com, stern@rowland.harvard.edu Subject: Re: [PATCH locking/Documentation 1/2] Add note of release-acquire store vulnerability Message-ID: <20160930055352.GC22004@tardis.cn.ibm.com> References: <20160929155401.GA5097@linux.vnet.ibm.com> <20160929155817.GB5016@twins.programming.kicks-ass.net> <20160929160307.GT13862@arm.com> <20160929164353.GX14933@linux.vnet.ibm.com> <20160929171036.GV13862@arm.com> <20160929172322.GZ14933@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="/unnNtmY43mpUSKx" Content-Disposition: inline In-Reply-To: <20160929172322.GZ14933@linux.vnet.ibm.com> User-Agent: Mutt/1.7.0 (2016-08-17) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --/unnNtmY43mpUSKx Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Paul, On Thu, Sep 29, 2016 at 10:23:22AM -0700, Paul E. McKenney wrote: > On Thu, Sep 29, 2016 at 06:10:37PM +0100, Will Deacon wrote: > > On Thu, Sep 29, 2016 at 09:43:53AM -0700, Paul E. McKenney wrote: > > > On Thu, Sep 29, 2016 at 05:03:08PM +0100, Will Deacon wrote: > > > > On Thu, Sep 29, 2016 at 05:58:17PM +0200, Peter Zijlstra wrote: > > > > > On Thu, Sep 29, 2016 at 08:54:01AM -0700, Paul E. McKenney wrote: > > > > > > If two processes are related by a RELEASE+ACQUIRE pair, orderin= g can be > > > > > > broken if a third process overwrites the value written by the R= ELEASE > > > > > > operation before the ACQUIRE operation has a chance of reading = it. > > > > > > This commit therefore updates the documentation to call this vu= lnerability > > > > > > out explicitly. > > > > > >=20 > > > > > > Reported-by: Alan Stern > > > > > > Signed-off-by: Paul E. McKenney > > > > >=20 > > > > > > + However, please note that a chain of RELEASE+ACQUIRE pair= s may be > > > > > > + broken by a store by another thread that overwrites the R= ELEASE > > > > > > + operation's store before the ACQUIRE operation's read. > > > > >=20 > > > > > This is the powerpc lwsync quirk, right? Where the barrier disapp= ears > > > > > when it looses the store. > > > > >=20 > > > > > Or is there more to it? Its not entirely clear from the Changelog= , which > > > > > I feel should describe the reason for the behaviour. > > > >=20 > > > > If I've groked it correctly, it's for cases like: > > > >=20 > > > >=20 > > > > PO: > > > > Wx=3D1 > > > > WyRel=3D1 > > > >=20 > > > > P1: > > > > Wy=3D2 > > > >=20 > > > > P2: > > > > RyAcq=3D2 > > > > Rx=3D0 > > > >=20 > > > > Final value of y is 2. > > > >=20 > > > >=20 > > > > This is permitted on arm64. If you make P1's store a store-release,= then > > > > it's forbidden, but I suspect that's not generally true of the kern= el > > > > memory model. > > >=20 > > > That is the one! And to Peter's point, powerpc does the same for the > > > example as shown. However, on powerpc, upgrading P1's store to relea= se > > > has no effect because there is no earlier access for the resulting > > > lwsync to influence. For whatever it might be worth, C11 won't guara= ntee > > > ordering in that case, either. Nor will the current Linux-kernel mem= ory > > > model. (Yes, I did just try it to make sure. Why do you ask?) > > >=20 > > > So you guys are fishing for an expanded commit log, for example, like > > > the following? ;-) > > >=20 > > > Thanx, Paul > > >=20 > > > ---------------------------------------------------------------------= --- > > >=20 > > > If two processes are related by a RELEASE+ACQUIRE pair, ordering can = be > > > broken if a third process overwrites the value written by the RELEASE > > > operation before the ACQUIRE operation has a chance of reading it, for > > > example: > > >=20 > > > P0(int *x, int *y) > > > { > > > WRITE_ONCE(*x, 1); > > > smp_wmb(); > > > smp_store_release(y, 1); > > > } > > >=20 > > > P1(int *y) > > > { > > > smp_store_release(y, 2); > > > } > > >=20 > > > P2(int *x, int *y) > > > { > > > r1 =3D smp_load_acquire(y); > > > r2 =3D READ_ONCE(*x); > > > } > > >=20 > > > Both ARM and powerpc allow the "after the dust settles" outcome (r1= =3D2 && > > > r2=3D0), as does the current version of the early prototype Linux-ker= nel > > > memory model. > >=20 > > FWIW, ARM doesn't allow this and arm64 only allows it if P1 uses WRITE_= ONCE > > instead of store-release. >=20 > Good catch, apologies for the error. The following, then? >=20 > Thanx, Paul >=20 > ------------------------------------------------------------------------ >=20 > If two processes are related by a RELEASE+ACQUIRE pair, ordering can be > broken if a third process overwrites the value written by the RELEASE > operation before the ACQUIRE operation has a chance of reading it, for > example: >=20 > P0(int *x, int *y) > { > WRITE_ONCE(*x, 1); > smp_wmb(); ^^^^^^^^^^^ What is this smp_wmb() for? > smp_store_release(y, 1); > } >=20 > P1(int *y) > { > WRITE_ONCE(*y, 2); If we change this WRITE_ONCE to a relaxed atomic operation(e.g. xchg_relaxed(y, 2)), both herd and ppcmem said the exist-clause "y =3D 2 /\ 2:r1 =3D 2 /\ 2:r2 =3D 0" wouldn't be triggered on PPC. I guess we will get the same behavior on ARM/ARM64, Will? If a normal store could break chain, while a RmW atomic won't, do we want to call it out in the document and build our memory model around this? I asked because in spin_unlock_wait() fix, we kind of relied on this. So it's good for us to clarify it? Regards, Boqun > } >=20 > P2(int *x, int *y) > { > r1 =3D smp_load_acquire(y); > r2 =3D READ_ONCE(*x); > } >=20 > Both ARM and powerpc allow the "after the dust settles" outcome (r1=3D2 && > r2=3D0), as does the current version of the early prototype Linux-kernel > memory model. >=20 --/unnNtmY43mpUSKx Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEcBAABCAAGBQJX7f3tAAoJEEl56MO1B/q4YIIH/3HY7bEVYueSAOGZyIQjzo3I 1CtyulfFNS4h+811kHft6fwytdgG7BCmOBzH1+vlmA3ATuocIKfTfVPB2DmLMgSs karJYSoHNAxIUaqP6C2Yy2qljrgKEIYOls8+adbHfnIwyY4hVoYpAj5OT3X4dsQk /OEJVmFwAd4jMoqiEDdnPgndoLUA8zbXl7xcvyZsBc5m1xU6ySwBguKM7Cq1SpQy N93/o72kJzvJWuUkuffw7rmWDsP2IifksntGOUmAsE37Z5xGxu3xa3J6RiCtnAph 1ZUguTZ/tSeyiGw7XAQNQ5x0TZRJzdDBsXnnzLJzrZ8okCZ7Op0mFicS4lC89t4= =cisN -----END PGP SIGNATURE----- --/unnNtmY43mpUSKx--