From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752071AbcJIPAG (ORCPT ); Sun, 9 Oct 2016 11:00:06 -0400 Received: from mga07.intel.com ([134.134.136.100]:44178 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751997AbcJIPAE (ORCPT ); Sun, 9 Oct 2016 11:00:04 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,466,1473145200"; d="scan'208";a="888249129" Date: Sun, 9 Oct 2016 17:59:59 +0300 From: Mika Westerberg To: Andy Shevchenko Cc: "Bacchewar, Nilesh" , "Krogerus, Heikki" , Linus Walleij , "linux-gpio@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH] pinctrl: intel: Configure GPIO chip IRQ as wakeup interrupts Message-ID: <20161009145959.GX30800@lahna.fi.intel.com> References: <1474499002-76446-1-git-send-email-nilesh.bacchewar@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo User-Agent: Mutt/1.7.0 (2016-08-17) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Oct 07, 2016 at 10:40:42PM +0300, Andy Shevchenko wrote: > On Fri, Oct 7, 2016 at 9:17 PM, Bacchewar, Nilesh > wrote: > > Here, Its marking GPIO controller IRQ line as wake capable not GPIO lines. > > AFAIU this is called per (GPIO) pin which is IRQ enabled. > > Imagine a case when you have more than one such pin. > > 1. Set IRQ wake for pin 1 > 2. Set IRQ wake for pin 2 (assume that is pin under the question) > 3. Unset IRQ wake for pin 1 (for some reason) > 4. Global pinctrl IRQ wake is unset. Resulting same issue as before. > > What did I miss above? enable/disable_irq_wake() include reference count.