From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756322AbcJNM6z (ORCPT ); Fri, 14 Oct 2016 08:58:55 -0400 Received: from down.free-electrons.com ([37.187.137.238]:55798 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1756099AbcJNM6E (ORCPT ); Fri, 14 Oct 2016 08:58:04 -0400 Date: Fri, 14 Oct 2016 14:57:43 +0200 From: Maxime Ripard To: Icenowy Zheng Cc: wens@csie.org, Thierry Reding , Rob Herring , Russell King , linux-pwm@vger.kernel.org, devicetree , linux-kernel , linux-sunxi Subject: Re: [linux-sunxi] [PATCH 2/5] pwm: sun4i: Add support for PWM controller on sun6i SoCs Message-ID: <20161014125743.ykgeiqr4tynq7cmg@lukather> References: <20161012042059.40015-1-icenowy@aosc.xyz> <20161012042059.40015-2-icenowy@aosc.xyz> <1476259803.2317.2.camel@Nokia-N900> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="ywwdiqnquul56udz" Content-Disposition: inline In-Reply-To: <1476259803.2317.2.camel@Nokia-N900> User-Agent: Mutt/1.6.2-neo (2016-08-21) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --ywwdiqnquul56udz Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Wed, Oct 12, 2016 at 04:10:03PM +0800, Icenowy Zheng wrote: > > On Wed, Oct 12, 2016 at 12:20 PM, Icenowy Zheng wrot= e: > > > The PWM controller in A31 is different with other Allwinner SoCs, with > > > a control register per channel (in other SoCs the control register is > > > shared), and each channel are allocated 16 bytes of address (but only= 8 > > > bytes are used.). The register map in one channel is just like a > > > single-channel A10 PWM controller, however, A31 have a different > > > prescaler table than other SoCs. > > >=20 > > > In order to use the driver for all 4 channels, device nodes should be > > > created per channel. > >=20 > > I think Maxime wants you to support the different register offsets > > in this driver, and have all 4 channels in the same device (node). >=20 > I think that will make the code much more complex... And in > hardware there may also be 4 controllers... as the register is > aligned at 0x10. You also have to think about it the other way around. This is exposed everywhere as a single device. There may be some undocumented registers hidden somewhere in the memory space of that device. How would you deal with that without touching the device tree? Exposing this as a single device is the best solution both from the philosophical point of view, but also from a maintainance aspect. Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --ywwdiqnquul56udz Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIcBAEBCAAGBQJYANZHAAoJEBx+YmzsjxAg6mAP/jnr4ou1rZagM9NiKUuTr7Zf ZOb1VQrb3oItIKCwXgh3ChF+YB9gIg0dx6OydabmJuUuroNVj8hLtlWc2wcxnlxJ tXA2s+97kI8Zc4jOag0zUL6xJiP9IIF49TAJmAQwQCbzkfSDu9eZpPjIqQWvbzW5 IkZRPirNquJt+HJR7INdiZdm6RVtqtf6u0PoA5+IMjwN/oahgO9hburcKcQMPWOs le6DvosV0FqSaQOSRYC3QvknOQAUJu0VLhuJq20XHpxtYCUWZHTqXRH77S0YdQUq 6Dsyz9RPlr4yLofcH3u48xM7JJ3RiCoodQb1YmYqkR0mUkXuX+7uo8nm24AqEz0o y7NvpD2Q2Y+rF7wbquda9miBSU7ee96yYg82QtxfPOoe7eAJhv2j4Ya5PXYodvX6 ygFbuzADApqyX6CCwIfNVnKssfo44q5y0t7GyBMmPzEah4qDfROAZ/mgTE47KQO6 xRSai9vs3yLNPGjAVJfMUks2m5VUD9y/RTS9y8Gyg2/MKFERPTzdcNedyK/iRJkF KVgD+5mYLFc5a3TbFha2Jkpee9/vHqVF1TxeU2j/Hh7RV9TTBy5CGLfslussJJDI 3uBmrnaou71Mfa9hYpxVfZ7P/Ng2UhJZ5ZeEZSlgscuywh/IQUy0VcZtX1hrdKLP C1mEpUOrVoGhDp29k1Ji =y3wl -----END PGP SIGNATURE----- --ywwdiqnquul56udz--