From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934884AbcJUP1v (ORCPT ); Fri, 21 Oct 2016 11:27:51 -0400 Received: from mout.kundenserver.de ([212.227.17.24]:52323 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933628AbcJUP1s (ORCPT ); Fri, 21 Oct 2016 11:27:48 -0400 From: Arnd Bergmann To: Daniel Vetter , Jani Nikula Cc: Zhi Wang , Zhenyu Wang , Arnd Bergmann , David Airlie , Chris Wilson , igvt-g-dev@ml01.01.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] drm/i915/gvt: fix compilation Date: Fri, 21 Oct 2016 17:25:50 +0200 Message-Id: <20161021152620.3324407-2-arnd@arndb.de> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20161021152620.3324407-1-arnd@arndb.de> References: <20161021152620.3324407-1-arnd@arndb.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Provags-ID: V03:K0:3hPYIlrbDKYCjvNVv/kGt7v44LjRSzw5bO/NIWeAXB2WyIQsOWs HkFfBi/pzMWDlJzb/8LB6hs2GjlOCRybeEfTEI1DvVZuWZbq6xrGkYHJY/xFhc+cHmd32Q0 djy4xQkijgkS/TbuRNjioJRZKolqiCsKGckYSOPbrx1TJtz1+PoWIRqd8m3Pu6pduMc3pRS 9mX/FkT3ztB6BcbINRBAA== X-UI-Out-Filterresults: notjunk:1;V01:K0:Nd0caVp/DaA=:H7qzIXQMagEwF30RAlHlJl Iua+Onn6OmLcgrompTkynIiDWGJ3uWy8qgavdTLDdJl6Zsrrpx/N29kSBGihvETgJfOfA+TL+ mU6t2t3T/W7iA//+HpYK2vdgetE87JFNYc1kQYBzJCtxh5mOpYRqrnjFeA2D0JBLNtOCFbtjV ujGn8fT1GHP8WIhQ9HzA7sfDPmN1Nf50Foo8YDjNobed1daoSOq8JTzCSZnaBWf2zz4Pl3hCM HwQjZEiHIbz9r+3cweg83Zis6NR416qmNpdgnJ+HtbNwXelPUI7zLO83d+t5ZAz1XQL8rUlWS XDUNzpppjEed0KAWG6DjOzCqehp5DLDFyk51FL7hYKtaxpgzN48mtwTXpSU8ThYttlyR36y/D L1LL1XYW3OYo48RVkaJWV3JzYan+GuC0KzGzyrXc2xxezsBZyzf+bTd3cSMGbq26L7djXjRaA xb7AY3WO/HpW21cKL6rinx+a2Xm0Es++Ac1kka5UaD0zOKmYaomtaxHT07L9Q5+m1N4ioGxiS 80j1yysqyG45+NUWLx/81aIYyqhHzeByXlc7AWuL8ZDlRGmG2ljdAGBljfd8ZmdAp8tsxWHUu wtlJg1ZxtWPkq+2CBMglx/8SDbFbdnAynSRWbI0VQkOaZ9UZU5Dw5ba76J5CorcjanSHmCEb/ VjyEfZFVMfBvqYr1+mB8gYD3FOF/ZekbYjhKUEwmxL4SzCATGaFop/j7MGWjxwlaeEs76+jyE mycEL5HUdJAUKeIf Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Two functions in the newly added gvt render code are obviously broken, as they reference a variable without initialization and don't reference another variable at all: drivers/gpu/drm/i915/gvt/render.c: In function ‘intel_gvt_load_render_mmio’: drivers/gpu/drm/i915/gvt/render.c:148:13: error: ‘offset.reg’ may be used uninitialized in this function [-Werror=maybe-uninitialized] drivers/gpu/drm/i915/gvt/render.c: In function ‘intel_gvt_restore_render_mmio’: drivers/gpu/drm/i915/gvt/render.c:185:13: error: ‘offset.reg’ may be used uninitialized in this function [-Werror=maybe-uninitialized] This is probably not a correct fix, but it gets us a clean build by removing the unused arrays and initializing the offset variable to something that potentially might be correct. Fixes: 178657139307 ("drm/i915/gvt: vGPU context switch") Signed-off-by: Arnd Bergmann --- drivers/gpu/drm/i915/gvt/render.c | 25 +++---------------------- 1 file changed, 3 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c index feebb65ba641..79e112288065 100644 --- a/drivers/gpu/drm/i915/gvt/render.c +++ b/drivers/gpu/drm/i915/gvt/render.c @@ -147,29 +147,20 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id) { struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; i915_reg_t offset, l3_offset; - u32 regs[] = { - [RCS] = 0xc800, - [VCS] = 0xc900, - [VCS2] = 0xca00, - [BCS] = 0xcc00, - [VECS] = 0xcb00, - }; int i; - if (WARN_ON(ring_id >= ARRAY_SIZE(regs))) - return; - if (!IS_SKYLAKE(dev_priv)) return; for (i = 0; i < 64; i++) { + offset.reg = i * 4; gen9_render_mocs[ring_id][i] = I915_READ(offset); I915_WRITE(offset, vgpu_vreg(vgpu, offset)); POSTING_READ(offset); - offset.reg += 4; } if (ring_id == RCS) { + offset.reg = 64 * 4; l3_offset.reg = 0xb020; for (i = 0; i < 32; i++) { gen9_render_mocs_L3[i] = I915_READ(l3_offset); @@ -184,26 +175,16 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id) { struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; i915_reg_t offset, l3_offset; - u32 regs[] = { - [RCS] = 0xc800, - [VCS] = 0xc900, - [VCS2] = 0xca00, - [BCS] = 0xcc00, - [VECS] = 0xcb00, - }; int i; - if (WARN_ON(ring_id >= ARRAY_SIZE(regs))) - return; - if (!IS_SKYLAKE(dev_priv)) return; for (i = 0; i < 64; i++) { + offset.reg = i * 4; vgpu_vreg(vgpu, offset) = I915_READ(offset); I915_WRITE(offset, gen9_render_mocs[ring_id][i]); POSTING_READ(offset); - offset.reg += 4; } if (ring_id == RCS) { -- 2.9.0