From: Catalin Marinas <catalin.marinas@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, mark.rutland@arm.com,
ryan.arnold@linaro.org, sid@reserved-bit.com, aph@redhat.com,
will.deacon@arm.com, linux-kernel@vger.kernel.org,
adhemerval.zanella@linaro.org, dave.martin@arm.com
Subject: Re: [PATCH v3 4/9] arm64: cpufeature: Document the rules of safe value for features
Date: Fri, 6 Jan 2017 12:30:11 +0000 [thread overview]
Message-ID: <20170106123011.GB12863@e104818-lin.cambridge.arm.com> (raw)
In-Reply-To: <1483552147-9605-5-git-send-email-suzuki.poulose@arm.com>
On Wed, Jan 04, 2017 at 05:49:02PM +0000, Suzuki K. Poulose wrote:
> --- a/arch/arm64/include/asm/cpufeature.h
> +++ b/arch/arm64/include/asm/cpufeature.h
> @@ -29,7 +29,21 @@
> #include <linux/jump_label.h>
> #include <linux/kernel.h>
>
> -/* CPU feature register tracking */
> +/*
> + * CPU feature register tracking
> + *
> + * The safe value of a CPUID feature field is dependent on the implications
> + * of the values assigned to it by the architecture. Based on the relationship
> + * between the values, the features are classified into 3 types.
> + *
> + * a) LOWER_SAFE - The value 'n+1' indicates, value 'n' and some
> + * additional features. (where n >= 0). The smaller value (n) is
> + * considered safer in this case.
> + * b) HIGHER_SAFE - The value 'n+1' is safer than 'n' (for n>= 0).
> + * c) EXACT - If the values of the feature don't have any relationship,
> + * a predefined safe value is used.
> + */
I don't think this text fully describes what is actually compared. You
could say something that the lowest value of all the CPUs is chosen for
LOWER_SAFE, highest for HIGHER_SAFE and it is expected that all CPUs
have the same value for a field when EXACT is specified.
--
Catalin
next prev parent reply other threads:[~2017-01-06 12:31 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-04 17:48 [PATCH v3 0/9] arm64: Expose CPUID registers via emulation Suzuki K Poulose
2017-01-04 17:48 ` [PATCH v3 1/9] arm64: cpufeature: treat unknown fields as RES0 Suzuki K Poulose
2017-01-05 17:08 ` Catalin Marinas
2017-01-04 17:49 ` [PATCH v3 2/9] arm64: cpufeature: remove explicit RAZ fields Suzuki K Poulose
2017-01-05 17:09 ` Catalin Marinas
2017-01-04 17:49 ` [PATCH v3 3/9] arm64: cpufeature: Cleanup feature bit tables Suzuki K Poulose
2017-01-05 17:18 ` Catalin Marinas
2017-01-04 17:49 ` [PATCH v3 4/9] arm64: cpufeature: Document the rules of safe value for features Suzuki K Poulose
2017-01-06 12:30 ` Catalin Marinas [this message]
2017-01-09 10:43 ` Suzuki K Poulose
2017-01-09 12:04 ` Catalin Marinas
2017-01-04 17:49 ` [PATCH v3 5/9] arm64: cpufeature: Define helpers for sys_reg id Suzuki K Poulose
2017-01-05 17:26 ` Catalin Marinas
2017-01-04 17:49 ` [PATCH v3 6/9] arm64: Add helper to decode register from instruction Suzuki K Poulose
2017-01-05 17:29 ` Catalin Marinas
2017-01-04 17:49 ` [PATCH v3 7/9] arm64: cpufeature: Track user visible fields Suzuki K Poulose
2017-01-05 18:06 ` Catalin Marinas
2017-01-06 11:18 ` Suzuki K Poulose
2017-01-04 17:49 ` [PATCH v3 8/9] arm64: cpufeature: Expose CPUID registers by emulation Suzuki K Poulose
2017-01-05 18:39 ` Catalin Marinas
2017-01-04 17:49 ` [PATCH v3 9/9] arm64: Documentation - Expose CPU feature registers Suzuki K Poulose
2017-01-06 12:16 ` Catalin Marinas
2017-01-09 10:59 ` Suzuki K Poulose
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