From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751421AbdAPGc6 (ORCPT ); Mon, 16 Jan 2017 01:32:58 -0500 Received: from mailout3.samsung.com ([203.254.224.33]:42944 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751009AbdAPGbp (ORCPT ); Mon, 16 Jan 2017 01:31:45 -0500 X-AuditID: b6c32a59-f79c56d000006d2c-02-587c68cea566 From: Jaehoon Chung To: linux-pci@vger.kernel.org Cc: bhelgaas@google.com, krzk@kernel.org, linux-kernel@vger.kernel.org, jingoohan1@gmail.com, javier@osg.samsung.com, kgene@kernel.org, linux-samsung-soc@vger.kernel.org, cpgs@samsung.com, Jaehoon Chung Subject: [PATCH V3 4/5] PCI: exynos: Use the bitops API to operate the bit shifting Date: Mon, 16 Jan 2017 15:31:37 +0900 Message-id: <20170116063138.25805-5-jh80.chung@samsung.com> X-Mailer: git-send-email 2.10.2 In-reply-to: <20170116063138.25805-1-jh80.chung@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrEKsWRmVeSWpSXmKPExsWy7bCmpu65jJoIg5072CyWNGVYvDykafHm 7Romixu/2lgtVnyZyW7R//g1s8X58xvYLS7vmsNmcXbecTaLGef3MTlweeycdZfdY8GmUo9N qzrZPLb0A3l9W1YxenzeJBfAFpVqk5GamJJapJCal5yfkpmXbqvkHRzvHG9qZmCoa2hpYa6k kJeYm2qr5OIToOuWmQN0l5JCWWJOKVAoILG4WEnfzqYov7QkVSEjv7jEVina0NBIz9DAXM/I yEjPxDjWysgUqCQhNWP3jsPsBQslKu4/Wc3WwLhcpIuRg0NCwERi2YqkLkZOIFNM4sK99Wxd jFwcQgJLGSVeHNrFDOG0M0nsXHWcHaLKROL4/gPsEIk5jBKXWnuhWn4wSjx52M8KUsUmoCOx /dtxJhBbREBW4uPlPWBFzAIvGSV+Nj8HGyUsECox88h7sCIWAVWJiZdPsoHYvALWEsu6/zJB rJOXWHj+CJjNKWAjMfnAcrCbJAS62SXWb7rKAvGErMSmA8wQ9S4Si5c2Q50qLPHq+BYoW1ri 79JbjFC9jBL/vmxkg3B6GCVubV0Ntc1Y4v6De2CTmAX4JHp/P2GCWMAr0dEmBFHiIbG6bwlU 2FHi/okCiO/7GSUe3ethncAos4CRYRWjWGpBcW56arFpgalecWJucWleul5yfu4mRnB60orc wXhlZtAhRgEORiUe3gU7qiOEWBPLiitzDzFKcDArifBOTKmJEOJNSaysSi3Kjy8qzUktPsRo CgynicxSosn5wNSZVxJvaGJmaGJkCYTmhuZK4rwLKqwjhATSE0tSs1NTC1KLYPqYODilGhh9 xLYu/FP44zSfl/qPTefyJaLPe5ifbpm0I/XIn0MeL52W79RQ7TpUs+WKWkjH7rYO3RnvVR22 VQaFfb1+ZOPdsB+CstX2a98wpFut/+fvPfdYux6TZqis6ZKzy57lXdpo8lZxc6nWixvJpa+2 GbmFT7fserM+zXyZ1+qZ5o/tFZ7nxElv+/hJiaU4I9FQi7moOBEAhZaLEmUDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrPLMWRmVeSWpSXmKPExsVy+t9jQd2zGTURBis2mFksacqweHlI0+LN 2zVMFjd+tbFarPgyk92i//FrZovz5zewW1zeNYfN4uy842wWM87vY3Lg8tg56y67x4JNpR6b VnWyeWzpB/L6tqxi9Pi8SS6ALcrNJiM1MSW1SCE1Lzk/JTMv3VYpNMRN10JJIS8xN9VWKULX NyRISaEsMacUyDMyQAMOzgHuwUr6dgluGbt3HGYvWChRcf/JarYGxuUiXYycHBICJhLH9x9g h7DFJC7cW8/WxcjFISQwi1Fi7e63rBDOD0aJpZNXsIFUsQnoSGz/dpwJxBYRkJX4eHkPWAez wEtGiY7zH1hAEsICoRIzj7wHK2IRUJWYePkkWDOvgLXEsu6/TBDr5CUWnj8CZnMK2EhMPrCc GcQWAqrZ3XWeaQIj7wJGhlWMEqkFyQXFSem5Rnmp5XrFibnFpXnpesn5uZsYwYH/THoH4+Fd 7ocYBTgYlXh4F+yojhBiTSwrrsw9xCjBwawkwjsxpSZCiDclsbIqtSg/vqg0J7X4EKMp0GET maVEk/OBUZlXEm9oYm5ibmxgYW5paWKkJM7bOPtZuJBAemJJanZqakFqEUwfEwenVAOjVUZF /hS5qN771es+H5tgomzd/FykZktvjqX20uLZ26xalt08Xb591SER+WbvyJJZMvlflpz88nVR p0ndSjUlmRUrjFXzXxy5OaMxV61np//E7il7087or9qlUp7Hy2N4luFYeGbmjjVr2e97mWs/ Tm1bdeRYzEbjh0qf2up3V0Vsy4hlkJFRYinOSDTUYi4qTgQAtGYnRJICAAA= X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170116063141epcas5p3717d40cea33d34b715b6c0016c10ab16 X-Msg-Generator: CA X-Sender-IP: 203.254.230.27 X-Local-Sender: =?UTF-8?B?7KCV7J6s7ZuIG1RpemVuIFBsYXRmb3JtIExhYihTL1fshLw=?= =?UTF-8?B?7YSwKRvsgrzshLHsoITsnpAbUzUo7LGF7J6EKS/ssYXsnoQ=?= X-Global-Sender: =?UTF-8?B?SmFlaG9vbiBDaHVuZxtUaXplbiBQbGF0Zm9ybSBMYWIuG1Nh?= =?UTF-8?B?bXN1bmcgRWxlY3Ryb25pY3MbUzUvU2VuaW9yIEVuZ2luZWVy?= X-Sender-Code: =?UTF-8?B?QzEwG1NUQUYbQzEwVjgxMTE=?= CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-HopCount: 7 X-CMS-RootMailID: 20170116063141epcas5p3717d40cea33d34b715b6c0016c10ab16 X-RootMTR: 20170116063141epcas5p3717d40cea33d34b715b6c0016c10ab16 References: <20170116063138.25805-1-jh80.chung@samsung.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Just use the bitops api to operate the bit. Signed-off-by: Jaehoon Chung Reviewed-by: Pankaj Dubey Acked-by: Krzysztof Kozlowski --- Changelog on V3: - None Changelog on V2: - None drivers/pci/host/pci-exynos.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c index 6255294..c5892c2 100644 --- a/drivers/pci/host/pci-exynos.c +++ b/drivers/pci/host/pci-exynos.c @@ -40,19 +40,19 @@ struct exynos_pcie { /* PCIe ELBI registers */ #define PCIE_IRQ_PULSE 0x000 -#define IRQ_INTA_ASSERT (0x1 << 0) -#define IRQ_INTB_ASSERT (0x1 << 2) -#define IRQ_INTC_ASSERT (0x1 << 4) -#define IRQ_INTD_ASSERT (0x1 << 6) +#define IRQ_INTA_ASSERT BIT(0) +#define IRQ_INTB_ASSERT BIT(2) +#define IRQ_INTC_ASSERT BIT(4) +#define IRQ_INTD_ASSERT BIT(6) #define PCIE_IRQ_LEVEL 0x004 #define PCIE_IRQ_SPECIAL 0x008 #define PCIE_IRQ_EN_PULSE 0x00c #define PCIE_IRQ_EN_LEVEL 0x010 -#define IRQ_MSI_ENABLE (0x1 << 2) +#define IRQ_MSI_ENABLE BIT(2) #define PCIE_IRQ_EN_SPECIAL 0x014 #define PCIE_PWR_RESET 0x018 #define PCIE_CORE_RESET 0x01c -#define PCIE_CORE_RESET_ENABLE (0x1 << 0) +#define PCIE_CORE_RESET_ENABLE BIT(0) #define PCIE_STICKY_RESET 0x020 #define PCIE_NONSTICKY_RESET 0x024 #define PCIE_APP_INIT_RESET 0x028 @@ -61,7 +61,7 @@ struct exynos_pcie { #define PCIE_ELBI_LTSSM_ENABLE 0x1 #define PCIE_ELBI_SLV_AWMISC 0x11c #define PCIE_ELBI_SLV_ARMISC 0x120 -#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21) +#define PCIE_ELBI_SLV_DBI_ENABLE BIT(21) /* PCIe Purple registers */ #define PCIE_PHY_GLOBAL_RESET 0x000 @@ -79,27 +79,27 @@ struct exynos_pcie { #define PCIE_PHY_DCC_FEEDBACK 0x014 #define PCIE_PHY_PLL_DIV_1 0x05c #define PCIE_PHY_COMMON_POWER 0x064 -#define PCIE_PHY_COMMON_PD_CMN (0x1 << 3) +#define PCIE_PHY_COMMON_PD_CMN BIT(3) #define PCIE_PHY_TRSV0_EMP_LVL 0x084 #define PCIE_PHY_TRSV0_DRV_LVL 0x088 #define PCIE_PHY_TRSV0_RXCDR 0x0ac #define PCIE_PHY_TRSV0_POWER 0x0c4 -#define PCIE_PHY_TRSV0_PD_TSV (0x1 << 7) +#define PCIE_PHY_TRSV0_PD_TSV BIT(7) #define PCIE_PHY_TRSV0_LVCC 0x0dc #define PCIE_PHY_TRSV1_EMP_LVL 0x144 #define PCIE_PHY_TRSV1_RXCDR 0x16c #define PCIE_PHY_TRSV1_POWER 0x184 -#define PCIE_PHY_TRSV1_PD_TSV (0x1 << 7) +#define PCIE_PHY_TRSV1_PD_TSV BIT(7) #define PCIE_PHY_TRSV1_LVCC 0x19c #define PCIE_PHY_TRSV2_EMP_LVL 0x204 #define PCIE_PHY_TRSV2_RXCDR 0x22c #define PCIE_PHY_TRSV2_POWER 0x244 -#define PCIE_PHY_TRSV2_PD_TSV (0x1 << 7) +#define PCIE_PHY_TRSV2_PD_TSV BIT(7) #define PCIE_PHY_TRSV2_LVCC 0x25c #define PCIE_PHY_TRSV3_EMP_LVL 0x2c4 #define PCIE_PHY_TRSV3_RXCDR 0x2ec #define PCIE_PHY_TRSV3_POWER 0x304 -#define PCIE_PHY_TRSV3_PD_TSV (0x1 << 7) +#define PCIE_PHY_TRSV3_PD_TSV BIT(7) #define PCIE_PHY_TRSV3_LVCC 0x31c static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg) -- 2.10.2