From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750812AbdAWF2B (ORCPT ); Mon, 23 Jan 2017 00:28:01 -0500 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:45607 "EHLO out1-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750703AbdAWF17 (ORCPT ); Mon, 23 Jan 2017 00:27:59 -0500 X-ME-Sender: X-Sasl-enc: I3xcWgxXRWn8wUOTkY6te9OZUWnEadWxrNQ9iOhnFJu+ 1485149278 From: Andrew Jeffery To: Joel Stanley Cc: Andrew Jeffery , Rob Herring , Mark Rutland , Russell King , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH] aspeed: dts: g5: Update GPIO pin range to mux extra banks Date: Mon, 23 Jan 2017 15:57:45 +1030 Message-Id: <20170123052745.9575-1-andrew@aj.id.au> X-Mailer: git-send-email 2.9.3 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Aspeed GPIO driver recently gained support for banks Y, Z, AA, AB and AC. Update the devicetree so GPIO requests for these pins are routed via pinmux, else the export succeeds but the GPIOs are non-functional. Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed-g5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index b664fe380936..a9305b964b11 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -920,8 +920,8 @@ compatible = "aspeed,ast2500-gpio"; reg = <0x1e780000 0x1000>; interrupts = <20>; - gpio-ranges = <&pinctrl 0 0 220>; interrupt-controller; + gpio-ranges = <&pinctrl 0 0 232>; }; timer: timer@1e782000 { -- 2.9.3