From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754511AbdA0I1i (ORCPT ); Fri, 27 Jan 2017 03:27:38 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:44829 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754231AbdA0I1H (ORCPT ); Fri, 27 Jan 2017 03:27:07 -0500 Date: Fri, 27 Jan 2017 09:17:12 +0100 From: Maxime Ripard To: Icenowy Zheng Cc: Srinivas Kandagatla , Rob Herring , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: Re: [PATCH 1/2] nvmem: sunxi-sid: add support for H3 and A64's SID controller Message-ID: <20170127081712.x2hprtpo2aolungc@lukather> References: <20170126113345.33686-1-icenowy@aosc.xyz> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="saqtkn6gx2s3ehzf" Content-Disposition: inline In-Reply-To: <20170126113345.33686-1-icenowy@aosc.xyz> User-Agent: Mutt/1.6.2-neo (2016-08-21) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --saqtkn6gx2s3ehzf Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Thu, Jan 26, 2017 at 07:33:44PM +0800, Icenowy Zheng wrote: > H3 and A64 SoCs have a bigger SID controller, which has its direct read > address at 0x200 position in the SID block, not 0x0. >=20 > Also, H3 SID controller has some silicon bug that makes the direct read > value wrong at first, add code to workaround the bug. (This bug has > already been fixed on A64 and later SoCs) >=20 > Signed-off-by: Icenowy Zheng > --- > .../bindings/nvmem/allwinner,sunxi-sid.txt | 22 +++- > drivers/nvmem/sunxi_sid.c | 112 +++++++++++++++= ++++-- > 2 files changed, 123 insertions(+), 11 deletions(-) >=20 > diff --git a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.= txt b/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt > index d543ed3f5363..d7400c415338 100644 > --- a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt > +++ b/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt > @@ -1,8 +1,16 @@ > Allwinner sunxi-sid > =20 > Required properties: > -- compatible: "allwinner,sun4i-a10-sid" or "allwinner,sun7i-a20-sid" > -- reg: Should contain registers location and length > +- compatible: Should be one of the following (depending on your SoC): > + "allwinner,sun4i-a10-sid" > + "allwinner,sun7i-a20-sid" > + "allwinner,sun8i-h3-sid" > + "allwinner,sun50i-a64-sid" > + > +- reg: Should contain registers location and registers length, for A10 a= nd A20 > + SoCs the length is directly the length of SID; for H3, A64 and newer S= oCs > + the length should be the sum of the length of SID and the offset of th= e value > + (0x200). > =20 > =3D Data cells =3D > Are child nodes of qfprom, bindings of which as described in > @@ -19,3 +27,13 @@ Example for sun7i: > compatible =3D "allwinner,sun7i-a20-sid"; > reg =3D <0x01c23800 0x200> > }; > + > +Example for sun8i-h3: > + sid@01c14000 { > + compatible =3D "allwinner,sun8i-h3-sid"; > + /* > + * The length of SID on H3 is 0x100 bytes, add the value offset > + * 0x200, so the total length should be 0x300. > + */ > + reg =3D <0x01c14000 0x300>; No, it should be the size of the memory region used and documented for that device, ie 1kB (0x400) in the H3 case, just like any other reg property. > + }; > diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c > index 1567ccca8de3..2e327a66a938 100644 > --- a/drivers/nvmem/sunxi_sid.c > +++ b/drivers/nvmem/sunxi_sid.c > @@ -20,10 +20,28 @@ > #include > #include > #include > +#include > #include > #include > #include > =20 > +/* Registers and special values for doing register-based SID readout on = H3 */ > +#define SUN8I_SID_PRCTL 0x40 > +#define SUN8I_SID_RDKEY 0x60 > + > +#define SUN8I_SID_OP_LOCK 0xAC > +#define SUN8I_SID_OFFSET_MASK 0x1FF > +#define SUN8I_SID_OFFSET_SHIFT 16 > +#define SUN8I_SID_LOCK_SHIFT 8 > +#define SUN8I_SID_READ BIT(1) > + > +/* > + * For newer SoCs with a larger eFUSE, the bytes beyond the first 16 byt= es are > + * sparse, which makes it not suitable for adding randomness; legacy SoC= s' SID > + * have only 16 bytes, so we choose to use at most 16 bytes to add rando= mness. > + */ > +#define SUNXI_SID_MAX_RANDOMNESS_SIZE 16 > + > static struct nvmem_config econfig =3D { > .name =3D "sunxi-sid", > .read_only =3D true, > @@ -32,8 +50,14 @@ static struct nvmem_config econfig =3D { > .owner =3D THIS_MODULE, > }; > =20 > +struct sunxi_sid_cfg { > + u32 value_offset; > + bool need_register_readout; > +}; > + > struct sunxi_sid { > void __iomem *base; > + u32 value_offset; > }; > =20 > /* We read the entire key, due to a 32 bit read alignment requirement. S= ince we > @@ -46,7 +70,8 @@ static u8 sunxi_sid_read_byte(const struct sunxi_sid *s= id, > { > u32 sid_key; > =20 > - sid_key =3D ioread32be(sid->base + round_down(offset, 4)); > + sid_key =3D ioread32be(sid->base + sid->value_offset + > + round_down(offset, 4)); > sid_key >>=3D (offset % 4) * 8; > =20 > return sid_key; /* Only return the last byte */ > @@ -64,26 +89,77 @@ static int sunxi_sid_read(void *context, unsigned int= offset, > return 0; > } > =20 > +static int sun8i_sid_register_readout(const struct sunxi_sid *sid, > + const unsigned int word, > + u32 *out) > +{ > + u32 reg_val; > + unsigned long expire =3D jiffies + msecs_to_jiffies(250); > + > + /* Set word, lock access, and set read command */ > + reg_val =3D (word & SUN8I_SID_OFFSET_MASK) > + << SUN8I_SID_OFFSET_SHIFT; > + reg_val |=3D SUN8I_SID_OP_LOCK << SUN8I_SID_LOCK_SHIFT; > + reg_val |=3D SUN8I_SID_READ; > + writel(reg_val, sid->base + SUN8I_SID_PRCTL); > + > + do { > + reg_val =3D readl(sid->base + SUN8I_SID_PRCTL); > + } while (time_before(jiffies, expire) && (reg_val & SUN8I_SID_READ)); > + > + if (reg_val & SUN8I_SID_READ) > + return -EIO; > + > + if (out) > + *out =3D readl(sid->base + SUN8I_SID_RDKEY); > + writel(0, sid->base + SUN8I_SID_PRCTL); > + return 0; > +} > + > static int sunxi_sid_probe(struct platform_device *pdev) > { > struct device *dev =3D &pdev->dev; > struct resource *res; > struct nvmem_device *nvmem; > struct sunxi_sid *sid; > - int ret, i, size; > + int ret, i, size, randomness_size; > char *randomness; > + const struct sunxi_sid_cfg *cfg; > =20 > sid =3D devm_kzalloc(dev, sizeof(*sid), GFP_KERNEL); > if (!sid) > return -ENOMEM; > =20 > + cfg =3D of_device_get_match_data(dev); > + if (!cfg) > + return -EINVAL; > + sid->value_offset =3D cfg->value_offset; > + > res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); > sid->base =3D devm_ioremap_resource(dev, res); > if (IS_ERR(sid->base)) > return PTR_ERR(sid->base); > =20 > - size =3D resource_size(res) - 1; > - econfig.size =3D resource_size(res); > + size =3D resource_size(res) - cfg->value_offset; > + > + if (cfg->need_register_readout) { > + /* > + * H3's SID controller have a bug that the value at 0x200 > + * offset is not the correct value when the hardware is reset. > + * However, after doing a register-based read operation, the > + * value become right. > + * Do a full read operation here, but ignore its value > + * (as it's more fast to read by direct MMIO value than > + * with registers) > + */ > + for (i =3D 0; i < (size >> 2); i++) { > + ret =3D sun8i_sid_register_readout(sid, i, NULL); > + if (ret) > + return ret; > + } > + } > + > + econfig.size =3D size; > econfig.dev =3D dev; > econfig.reg_read =3D sunxi_sid_read; > econfig.priv =3D sid; > @@ -91,16 +167,17 @@ static int sunxi_sid_probe(struct platform_device *p= dev) > if (IS_ERR(nvmem)) > return PTR_ERR(nvmem); > =20 > - randomness =3D kzalloc(sizeof(u8) * (size), GFP_KERNEL); > + randomness_size =3D max(size, SUNXI_SID_MAX_RANDOMNESS_SIZE); > + randomness =3D kzalloc(sizeof(u8) * (randomness_size), GFP_KERNEL); Why is that change needed? Thanks, Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --saqtkn6gx2s3ehzf Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIcBAEBCAAGBQJYiwIDAAoJEBx+YmzsjxAgs1sP/Azxt1v4o6uyYO3YHuVnFrmH q7xg44Vvu8tDAdAGY62ew42OLMS8pFfOGsNzw3xRilrE+KMmcLXUgQal+uOfwF6/ g+jn/QUXAoBXNFIZzGFp095Sc1PY0Ym8EjjLGORU/sIRgCFrnrcfsk76uTk+kbg4 7MauZJmJDYps8xxYrnbsnUyimVm2ZvVyH+BC/ZPfQl/iBbVaWo6GYSwK3LdzN7xt Q7Ui7Cfw1NY/BTakRdVtaggYykkTw+gv8JdaxjJV/MAs55UQGql6m+btiztP/K5s lEap82ACjxMYrUDUBfWDfQuqumBp355ZdADKvuy8ZiR4UOCoc/FRgy8sZHWeZGOt BNBaXkGP510WVgYTpH1Vuvyp8xjyELFEUzNIC0glOaQnyJkGGj08hUp7I9XEHaCz HCNVYNoZk7dWRRI9Qp53GlmH62Jv+Qtyft3R+AXbQOYWy7JkL6AUAnYho7UEerZK aOoIzkUUTTobYWBphwdgnZ32UBJ1VWW6OQnMEElGFi+fLRmfN8fh5v++XLYY7bWa 5OwpQTzBx1hKMX2qC5HD7f8T+De0/Kc3hf0Dz60RdTSpGfV1PnVPeNmqDRy3XXRL z9sTWwnQrePipQauZiomPpk3bnSaTPXvh8Lays77z1GCAlwAKsBGoC46KsPKNNK6 JKpzPVDK96j1j8nJtesS =yPs5 -----END PGP SIGNATURE----- --saqtkn6gx2s3ehzf--