From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754488AbdA3U0J (ORCPT ); Mon, 30 Jan 2017 15:26:09 -0500 Received: from mail-qk0-f169.google.com ([209.85.220.169]:34988 "EHLO mail-qk0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754462AbdA3U0F (ORCPT ); Mon, 30 Jan 2017 15:26:05 -0500 Date: Mon, 30 Jan 2017 15:25:47 -0500 From: Sean Paul To: John Keeping Cc: Mark Yao , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, Chris Zhong , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 14/24] drm/rockchip: dw-mipi-dsi: ensure PHY is reset Message-ID: <20170130202547.GQ20076@art_vandelay> References: <20170129132444.25251-1-john@metanate.com> <20170129132444.25251-15-john@metanate.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170129132444.25251-15-john@metanate.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Jan 29, 2017 at 01:24:34PM +0000, John Keeping wrote: > Also don't power up the DSI host at this point since this is not > necessary in order to configure the PHY and we do so later when > selecting video or command mode. > Reviewed-by: Sean Paul > Signed-off-by: John Keeping > Reviewed-by: Chris Zhong > --- > v3: > - Add Chris' Reviewed-by > Unchanged in v2 > > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index c2e0ba96e0a0..5b3068e9e8db 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -397,7 +397,10 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) > return testdin; > } > > - dsi_write(dsi, DSI_PWR_UP, POWERUP); > + /* Start by clearing PHY state */ > + dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); > + dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR); > + dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); > > dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE | > VCO_RANGE_CON_SEL(vco) | > -- > 2.11.0.197.gb556de5.dirty > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Sean Paul, Software Engineer, Google / Chromium OS