From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751492AbdBAKYp (ORCPT ); Wed, 1 Feb 2017 05:24:45 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:32844 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751284AbdBAKYg (ORCPT ); Wed, 1 Feb 2017 05:24:36 -0500 Date: Wed, 1 Feb 2017 11:24:32 +0100 From: Daniel Vetter To: Chris Wilson Cc: linux-kernel@vger.kernel.org, intel-gfx@lists.freedesktop.org, lkml@pengaru.com, "# v4 . 10-rc1+" Subject: Re: [Intel-gfx] [PATCH v2] drm/i915: Flush untouched framebuffers before display on !llc Message-ID: <20170201102432.ju36fs2f6nz5v5f4@phenom.ffwll.local> Mail-Followup-To: Chris Wilson , linux-kernel@vger.kernel.org, intel-gfx@lists.freedesktop.org, lkml@pengaru.com, "# v4 . 10-rc1+" References: <20170109063240.GB9125@shells.gnugeneration.com> <20170109111932.6342-1-chris@chris-wilson.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170109111932.6342-1-chris@chris-wilson.co.uk> X-Operating-System: Linux phenom 4.8.0-1-amd64 User-Agent: NeoMutt/20161126 (1.7.1) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jan 09, 2017 at 11:19:32AM +0000, Chris Wilson wrote: > On a non-llc system, the objects are created with .cache_level = > CACHE_NONE and so the transition to uncached for scanout is a no-op. > However, if the object was never written to, it will still be in the CPU > domain (having been zeroed out by shmemfs). Those cachelines need to be > flushed prior to display. > > Reported-by: Vito Caputo > Fixes: a6a7cc4b7db6 ("drm/i915: Always flush the dirty CPU cache when pinning the scanout") > Signed-off-by: Chris Wilson > Cc: # v4.10-rc1+ > --- > drivers/gpu/drm/i915/i915_gem.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 76689b59fc90..bdb113ef8cfe 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -3514,7 +3514,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, > vma->display_alignment = max_t(u64, vma->display_alignment, alignment); > > /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */ > - if (obj->cache_dirty) { > + if (obj->cache_dirty || obj->base.write_domain == I915_GEM_DOMAIN_CPU) { Alternatively, should we set cache_dirty when initially allocating an object? Ofc only if cpu_cache_is_coherent, like we do in other places. Anyway, up to you which one you like more I'd say, this one looks correct too. Reviewed-by: Daniel Vetter > i915_gem_clflush_object(obj, true); > intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); > } > -- > 2.11.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch