From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752150AbdBJIIY (ORCPT ); Fri, 10 Feb 2017 03:08:24 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:34180 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751058AbdBJIIV (ORCPT ); Fri, 10 Feb 2017 03:08:21 -0500 Date: Fri, 10 Feb 2017 09:07:06 +0100 From: Maxime Ripard To: Icenowy Zheng Cc: Linus Walleij , Rob Herring , Chen-Yu Tsai , Catalin Marinas , Will Deacon , "linux-gpio@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-sunxi@googlegroups.com" Subject: Re: [PATCH 5/8] arm64: dts: allwinner: add R_PIO node Message-ID: <20170210080706.loofvr3mmctfa2mc@lukather> References: <20170208100009.29362-1-icenowy@aosc.xyz> <20170208100009.29362-5-icenowy@aosc.xyz> <20170208101458.du6ybqsw52ypzhzw@lukather> <39431486552126@web41j.yandex.ru> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="jwrinjwhek26djsn" Content-Disposition: inline In-Reply-To: <39431486552126@web41j.yandex.ru> User-Agent: Mutt/1.6.2-neo (2016-08-21) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --jwrinjwhek26djsn Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Feb 08, 2017 at 07:08:46PM +0800, Icenowy Zheng wrote: > 08.02.2017, 18:15, "Maxime Ripard" : > > On Wed, Feb 08, 2017 at 06:00:06PM +0800, Icenowy Zheng wrote: > >> =A0Allwinner A64 SoC has a R_PIO node like the one in H3. > >> > >> =A0Add the node as well as needed clocks and resets. > >> > >> =A0As there's no document for apb0_gates, I only added the R_PIO bit h= ere. > >> > >> =A0Signed-off-by: Icenowy Zheng > >> =A0--- > >> =A0=A0arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 40 +++++++++++++= ++++++++++++++ > >> =A0=A01 file changed, 40 insertions(+) > >> > >> =A0diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/a= rm64/boot/dts/allwinner/sun50i-a64.dtsi > >> =A0index 1c64ea2d23f9..4b0baa79554c 100644 > >> =A0--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > >> =A0+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > >> =A0@@ -98,6 +98,15 @@ > >> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0clock-output-nam= es =3D "osc32k"; > >> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0}; > >> > >> =A0+ apb0: apb0_clk { > >> =A0+ compatible =3D "fixed-factor-clock"; > >> =A0+ #clock-cells =3D <0>; > >> =A0+ clock-div =3D <1>; > >> =A0+ clock-mult =3D <1>; > >> =A0+ clocks =3D <&osc24M>; > >> =A0+ clock-output-names =3D "apb0"; > >> =A0+ }; > >> =A0+ > >> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0psci { > >> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0compatible =3D "= arm,psci-0.2"; > >> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0method =3D "smc"; > >> =A0@@ -392,5 +401,36 @@ > >> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0interrupts =3D , > >> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0; > >> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0}; > >> =A0+ > >> =A0+ apb0_gates: clk@1f01428 { > >> =A0+ compatible =3D "allwinner,sun50i-a64-apb0-gates-clk", > >> =A0+ "allwinner,sun4i-a10-gates-clk"; > >> =A0+ reg =3D <0x01f01428 0x4>; > >> =A0+ #clock-cells =3D <1>; > >> =A0+ clocks =3D <&apb0>; > >> =A0+ clock-indices =3D <0>; > >> =A0+ clock-output-names =3D "apb0_pio"; > >> =A0+ }; > >> =A0+ > >> =A0+ apb0_rst: reset@1f014b0 { > >> =A0+ reg =3D <0x01f014b0 0x4>; > >> =A0+ compatible =3D "allwinner,sun6i-a31-clock-reset"; > >> =A0+ #reset-cells =3D <1>; > >> =A0+ }; > > > > Please make a sunxi-ng driver for those clocks. >=20 > We have no enough materials to make such a CCU driver. >=20 > Clocks in CPUs are usually undocumented, and difficult to > be collected -- even the clk-sun50iw1.c in BSP do not have > all clocks in CPUs. That's unfortunate, but we can deal with that by simply extending the clocks we have. Nothing too complicated or unconvenient to deal with. > We should only make it sunxi-ng until it's fully discovered (all > functions in CPUs are functional). No, I expect that by 4.12 we have converted every users to sunxi-ng, PRCM included. Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --jwrinjwhek26djsn Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIcBAEBCAAGBQJYnXSqAAoJEBx+YmzsjxAgvCwP/jz6fMkzK82uE7uGoLJesacU HKbgwOjMPRJCmwKfmcoYckPr8xSWNPfkB16W1I2Fk3E8EyluSwWz15tKxvzrfeVf oLFlnsPzbl+xJAiRiABAw2XsSUoFwwppz7cxhwnbO2BNHqEJ6ogFIKercMz9YzEU dzO58Z7S/wQ/zjeDgxpNEO/IkyQJcqMBlQLOo4btmAKN4nACpaJx5tY1tLH6oGLH 2ugeM9ACmXwEbF2DB8W96/+xMd0pV22GqlEyRMGRXctRN8y6CD7iuY07BuWjC++I 974/nYdOW5FpE4bHGO4A6vuH9ljRMipsooZplgM4XsGPShBXEzKU+TW93OGp7vQ3 7qru94Iu1ocuZkhbc/ronrhwudkY8ArEa8cuLZO+1k+jUWk1vAan/a7VIcduzKTR 6LCjwcDePuFv2XpEvk/2pyxrKsLxvZWcjhXTZpOV6fDxFZozUSxet+3W7wctuGPF encnryj2yC/oIijt4CGdCiZTTOMAboHRgYyODXs5DDjn8dWDRasza5xtdtmnTBH4 oMklTnC5zN/IfipZDZpiJgxPRwS/JvFNx2kRFAu2jd3vdbJW9o60TJQ8GUVeX/NV +ycbMJM2V4AGhE9Rd2oEOfHFk/k4D111LnWxqMooF9zBQfth9JUD2/Jpy9GvyrEy XAGFNEdBB346QRQmpk54 =d7UZ -----END PGP SIGNATURE----- --jwrinjwhek26djsn--