From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932266AbdBPMzZ (ORCPT ); Thu, 16 Feb 2017 07:55:25 -0500 Received: from mail-wm0-f68.google.com ([74.125.82.68]:36113 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754722AbdBPMvb (ORCPT ); Thu, 16 Feb 2017 07:51:31 -0500 From: Corentin Labbe To: peppe.cavallaro@st.com, robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, alexandre.torgue@st.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, LABBE Corentin Subject: [PATCH 07/21] ARM: dts: sun8i-h3: add dwmac-sun8i ethernet driver Date: Thu, 16 Feb 2017 13:48:45 +0100 Message-Id: <20170216124859.14346-8-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170216124859.14346-1-clabbe.montjoie@gmail.com> References: <20170216124859.14346-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: LABBE Corentin The dwmac-sun8i is an ethernet MAC hardware that support 10/100/1000 speed. This patch enable the dwmac-sun8i on the Allwinner H3 SoC Device-tree. The SoC H3 have an internal PHY, so optionals syscon and ephy are set. Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sun8i-h3.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 9f91aaa..61d56d2 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -594,6 +594,31 @@ #size-cells = <0>; }; + emac: ethernet@1c30000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + }; + gic: interrupt-controller@01c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, -- 2.10.2