From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753676AbdBTPgk (ORCPT ); Mon, 20 Feb 2017 10:36:40 -0500 Received: from mail-db5eur01on0065.outbound.protection.outlook.com ([104.47.2.65]:47456 "EHLO EUR01-DB5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751329AbdBTPgg (ORCPT ); Mon, 20 Feb 2017 10:36:36 -0500 Authentication-Results: spf=pass (sender IP is 188.184.36.50) smtp.mailfrom=cern.ch; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=cern.ch; From: Adrian Fiergolski To: CC: , , , , , , Adrian Fiergolski Subject: [PATCH] spi: Add spi-bits-per-word binding. Date: Mon, 20 Feb 2017 16:35:12 +0100 Message-ID: <20170220153512.6563-1-adrian.fiergolski@cern.ch> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170217101151.hyzmz5a4lgdy7p5m> References: <20170217101151.hyzmz5a4lgdy7p5m> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [81.28.193.211] X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:188.184.36.50;IPV:NLI;CTRY:CH;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(7916002)(39850400002)(39840400002)(39410400002)(39450400003)(2980300002)(438002)(199003)(189002)(189998001)(48376002)(50466002)(47776003)(86362001)(50226002)(8936002)(33646002)(11926002)(8676002)(66066001)(246002)(2351001)(7636002)(7736002)(50986999)(356003)(305945005)(54906002)(106466001)(626004)(76176999)(36756003)(230783001)(5003940100001)(6116002)(3846002)(5660300001)(1076002)(6666003)(39060400002)(2950100002)(6916009)(92566002)(38730400002)(110136004)(2906002)(4326007)(74482002)(107886003)(49486002);DIR:OUT;SFP:1101;SCL:1;SRVR:DB6PR0601MB2696;H:CERNMX11.cern.ch;FPR:;SPF:Pass;PTR:cernmx11.cern.ch;A:1;MX:1;LANG:en; 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The last takes as an argument spi_device struct, which, in case of spidev, has bits_per_word set to 0. Thus, the spi_setup function will set it to default 8. Further, the same function will call __spi_validate_bits_per_word which will fail the whole registration for controllers not supporting 8 bit transfers (i.e. xilinx-spi). Signed-off-by: Adrian Fiergolski --- Documentation/devicetree/bindings/spi/spi-bus.txt | 40 ++++++++++++----------- drivers/spi/spi.c | 18 ++++++++++ 2 files changed, 39 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt index 4b1d6e7..8401741 100644 --- a/Documentation/devicetree/bindings/spi/spi-bus.txt +++ b/Documentation/devicetree/bindings/spi/spi-bus.txt @@ -43,26 +43,28 @@ cs3 : &gpio1 2 0 SPI slave nodes must be children of the SPI master node and can contain the following properties. -- reg - (required) chip select address of device. -- compatible - (required) name of SPI device following generic names - recommended practice. +- reg - (required) chip select address of device. +- compatible - (required) name of SPI device following generic names + recommended practice. - spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz. -- spi-cpol - (optional) Empty property indicating device requires - inverse clock polarity (CPOL) mode. -- spi-cpha - (optional) Empty property indicating device requires - shifted clock phase (CPHA) mode. -- spi-cs-high - (optional) Empty property indicating device requires - chip select active high. -- spi-3wire - (optional) Empty property indicating device requires - 3-wire mode. -- spi-lsb-first - (optional) Empty property indicating device requires - LSB first mode. -- spi-tx-bus-width - (optional) The bus width (number of data wires) that is - used for MOSI. Defaults to 1 if not present. -- spi-rx-bus-width - (optional) The bus width (number of data wires) that is - used for MISO. Defaults to 1 if not present. -- spi-rx-delay-us - (optional) Microsecond delay after a read transfer. -- spi-tx-delay-us - (optional) Microsecond delay after a write transfer. +- spi-cpol - (optional) Empty property indicating device requires + inverse clock polarity (CPOL) mode. +- spi-cpha - (optional) Empty property indicating device requires + shifted clock phase (CPHA) mode. +- spi-cs-high - (optional) Empty property indicating device requires + chip select active high. +- spi-3wire - (optional) Empty property indicating device requires + 3-wire mode. +- spi-lsb-first - (optional) Empty property indicating device requires + LSB first mode. +- spi-tx-bus-width - (optional) The bus width (number of data wires) that is + used for MOSI. Defaults to 1 if not present. +- spi-rx-bus-width - (optional) The bus width (number of data wires) that is + used for MISO. Defaults to 1 if not present. +- spi-rx-delay-us - (optional) Microsecond delay after a read transfer. +- spi-tx-delay-us - (optional) Microsecond delay after a write transfer. +- spi-bits-per-word - (optional) Word size for a data transfer. Defaults is 8 + if not present. Some SPI controllers and devices support Dual and Quad SPI transfer mode. It allows data in the SPI system to be transferred using 2 wires (DUAL) or 4 diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 656dd3e..57fe058 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -1594,6 +1594,17 @@ of_register_spi_device(struct spi_master *master, struct device_node *nc) } spi->max_speed_hz = value; + /* Device bits-per-word */ + if (!of_property_read_u32(nc, "spi-bits-per-word", &value)) { + if (value > 32) + dev_warn(&master->dev, + "bits-per-word %d not supported\n", + value); + else + spi->bits_per_word = value; + } + + /* Store a pointer to the node in the device structure */ of_node_get(nc); spi->dev.of_node = nc; @@ -1673,6 +1684,13 @@ static int acpi_spi_add_resource(struct acpi_resource *ares, void *data) spi->max_speed_hz = sb->connection_speed; + if (sb->data_bit_length > 32) + dev_warn(&master->dev, + "bits-per-word %d not supported\n", + sb->data_bit_length); + else + spi->bits_per_word = sb->data_bit_length; + if (sb->clock_phase == ACPI_SPI_SECOND_PHASE) spi->mode |= SPI_CPHA; if (sb->clock_polarity == ACPI_SPI_START_HIGH) -- 2.9.3