From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751734AbdB1GkW (ORCPT ); Tue, 28 Feb 2017 01:40:22 -0500 Received: from mx2.suse.de ([195.135.220.15]:38956 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751060AbdB1GkO (ORCPT ); Tue, 28 Feb 2017 01:40:14 -0500 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: arm@kernel.org Cc: linux-arm-kernel@lists.infradead.org, mp-cs@actions-semi.com, 96boards@ucrobotics.com, support@lemaker.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v3 19/25] dt-bindings: arm: cpus: Add S500 enable-method Date: Tue, 28 Feb 2017 07:35:29 +0100 Message-Id: <20170228063535.32069-20-afaerber@suse.de> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170228063535.32069-1-afaerber@suse.de> References: <20170228063535.32069-1-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Actions Semi S500 SoC requires a special secondary CPU boot procedure. Signed-off-by: Andreas Färber --- v3: new Documentation/devicetree/bindings/arm/cpus.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 698ad1f0..e3e1e2f 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -192,6 +192,7 @@ nodes to be present and contain the properties described below. "spin-table" # On ARM 32-bit systems this property is optional and can be one of: + "actions,s500-smp" "allwinner,sun6i-a31" "allwinner,sun8i-a23" "arm,realview-smp" -- 2.10.2