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From: Jerome Brunet <jbrunet@baylibre.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	Kevin Hilman <khilman@baylibre.com>,
	Carlo Caione <carlo@caione.org>
Cc: Jerome Brunet <jbrunet@baylibre.com>,
	linux-clk@vger.kernel.org, linux-amlogic@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH v2 3/9] clk: meson8b: put dividers and muxes in tables
Date: Thu,  9 Mar 2017 11:41:48 +0100	[thread overview]
Message-ID: <20170309104154.28295-4-jbrunet@baylibre.com> (raw)
In-Reply-To: <20170309104154.28295-1-jbrunet@baylibre.com>

Until now, there was only 1 divider and 1 mux declared for the meson8b
platform. With the ongoing work on various system, including audio, this
is about to change. Use the same approach as gates for dividers and muxes,
putting them in tables to fix the register address at runtime.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/meson8b.c | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index d1cc4d7cc8ff..2937443d4505 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -582,6 +582,14 @@ static struct clk_gate *const meson8b_clk_gates[] = {
 	&meson8b_ao_iface,
 };
 
+static struct clk_mux *const meson8b_clk_muxes[] = {
+	&meson8b_mpeg_clk_sel,
+};
+
+static struct clk_divider *const meson8b_clk_dividers[] = {
+	&meson8b_mpeg_clk_div,
+};
+
 static int meson8b_clkc_probe(struct platform_device *pdev)
 {
 	void __iomem *clk_base;
@@ -604,15 +612,21 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
 	/* Populate the base address for CPU clk */
 	meson8b_cpu_clk.base = clk_base;
 
-	/* Populate the base address for the MPEG clks */
-	meson8b_mpeg_clk_sel.reg = clk_base + (u32)meson8b_mpeg_clk_sel.reg;
-	meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg;
-
 	/* Populate base address for gates */
 	for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++)
 		meson8b_clk_gates[i]->reg = clk_base +
 			(u32)meson8b_clk_gates[i]->reg;
 
+	/* Populate base address for muxes */
+	for (i = 0; i < ARRAY_SIZE(meson8b_clk_muxes); i++)
+		meson8b_clk_muxes[i]->reg = clk_base +
+			(u32)meson8b_clk_muxes[i]->reg;
+
+	/* Populate base address for dividers */
+	for (i = 0; i < ARRAY_SIZE(meson8b_clk_dividers); i++)
+		meson8b_clk_dividers[i]->reg = clk_base +
+			(u32)meson8b_clk_dividers[i]->reg;
+
 	/*
 	 * register all clks
 	 * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
-- 
2.9.3

  parent reply	other threads:[~2017-03-09 10:51 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-09 10:41 [PATCH v2 0/9] clk: meson: update clock controller for audio support Jerome Brunet
2017-03-09 10:41 ` [PATCH v2 1/9] clk: meson: fix SET_PARM macro Jerome Brunet
2017-03-09 10:41 ` [PATCH v2 2/9] clk: meson: add missing const qualifiers on gate arrays Jerome Brunet
2017-03-09 10:41 ` Jerome Brunet [this message]
2017-03-21 23:10   ` [PATCH v2 3/9] clk: meson8b: put dividers and muxes in tables Michael Turquette
2017-03-09 10:41 ` [PATCH v2 4/9] clk: gxbb: " Jerome Brunet
2017-03-21 23:10   ` Michael Turquette
2017-03-09 10:41 ` [PATCH v2 5/9] clk: meson: mpll: add rw operation Jerome Brunet
2017-03-21 23:19   ` Michael Turquette
2017-03-09 10:41 ` [PATCH v2 6/9] clk: meson: gxbb: mpll: use " Jerome Brunet
2017-03-21 23:20   ` Michael Turquette
2017-03-09 10:41 ` [PATCH v2 7/9] clk: meson8b: add the mplls clocks 0, 1 and 2 Jerome Brunet
2017-03-21 23:21   ` Michael Turquette
2017-03-09 10:41 ` [PATCH v2 8/9] clk: meson: mpll: correct N2 maximum value Jerome Brunet
2017-03-09 10:41 ` [PATCH v2 9/9] dt-bindings: clk: gxbb: expose i2s output clock gates Jerome Brunet
2017-03-11  0:39 ` [PATCH v2 0/9] clk: meson: update clock controller for audio support Kevin Hilman
2017-03-27 19:52   ` Michael Turquette

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