From: Alexander Shishkin <alexander.shishkin@linux.intel.com>
To: Greg KH <greg@kroah.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>,
Chunyan Zhang <zhang.chunyan@linaro.org>,
laurent.fert@intel.com, linux-kernel@vger.kernel.org,
Alexander Shishkin <alexander.shishkin@linux.intel.com>
Subject: [QUEUED v20170314 2/3] intel_th: pci: Add Denverton SOC support
Date: Tue, 14 Mar 2017 13:32:41 +0200 [thread overview]
Message-ID: <20170314113242.2249-3-alexander.shishkin@linux.intel.com> (raw)
In-Reply-To: <20170314113242.2249-1-alexander.shishkin@linux.intel.com>
This adds Intel(R) Trace Hub PCI ID for Denverton SOC.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
---
drivers/hwtracing/intel_th/pci.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/hwtracing/intel_th/pci.c b/drivers/hwtracing/intel_th/pci.c
index 0bba384233..04bd57b010 100644
--- a/drivers/hwtracing/intel_th/pci.c
+++ b/drivers/hwtracing/intel_th/pci.c
@@ -85,6 +85,11 @@ static const struct pci_device_id intel_th_pci_id_table[] = {
PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa2a6),
.driver_data = (kernel_ulong_t)0,
},
+ {
+ /* Denverton */
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x19e1),
+ .driver_data = (kernel_ulong_t)0,
+ },
{ 0 },
};
--
2.11.0
next prev parent reply other threads:[~2017-03-14 11:33 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-14 11:32 [QUEUED v20170314 0/3] intel_th: Fixes for 4.11 Alexander Shishkin
2017-03-14 11:32 ` [QUEUED v20170314 1/3] intel_th: msu: Don't leak module refcount on failure to activate Alexander Shishkin
2017-03-14 11:32 ` Alexander Shishkin [this message]
2017-03-14 11:32 ` [QUEUED v20170314 3/3] intel_th: pci: Add Gemini Lake support Alexander Shishkin
2017-03-14 11:39 ` [QUEUED v20170314 0/3] intel_th: Fixes for 4.11 Alexander Shishkin
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