From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751185AbdCQMiv (ORCPT ); Fri, 17 Mar 2017 08:38:51 -0400 Received: from dliviu.plus.com ([80.229.23.120]:47192 "EHLO smtp.dudau.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751130AbdCQMis (ORCPT ); Fri, 17 Mar 2017 08:38:48 -0400 X-Greylist: delayed 3561 seconds by postgrey-1.27 at vger.kernel.org; Fri, 17 Mar 2017 08:38:47 EDT Date: Fri, 17 Mar 2017 10:43:39 +0000 From: Liviu Dudau To: "Luis R. Rodriguez" Cc: Bjorn Helgaas , Liviu Dudau , Lorenzo Pieralisi , "Paul E. McKenney" , Andy Lutomirski , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Wenrui Li , Gabriele Paoloni , Catalin Marinas , Shawn Lin , Will Deacon , Michal Simek , Thierry Reding , Tanmay Inamdar , linux-arch@vger.kernel.org, Pratyush Anand , Russell King , Jon Mason , Murali Karicheri , Arnd Bergmann , Bharat Kumar Gogada , Ray Jui , John Garry , Joao Pinto , Bjorn Helgaas , Mingkai Hu , Thomas Petazzoni , Jingoo Han , linux-kernel@vger.kernel.org, Stanimir Varbanov , Minghuan Lian , Zhou Wang , Roy Zang Subject: Re: [PATCH 02/20] PCI: fix pci_remap_iospace() remap attribute Message-ID: <20170317104339.GD24830@bart.dudau.co.uk> References: <20170227151436.18698-1-lorenzo.pieralisi@arm.com> <20170227151436.18698-3-lorenzo.pieralisi@arm.com> <20170316214844.GA17769@bhelgaas-glaptop.roam.corp.google.com> <20170317003321.GB28800@wotan.suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20170317003321.GB28800@wotan.suse.de> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Mar 17, 2017 at 01:33:21AM +0100, Luis R. Rodriguez wrote: > On Thu, Mar 16, 2017 at 04:48:44PM -0500, Bjorn Helgaas wrote: > > [+cc Luis] > > > > On Mon, Feb 27, 2017 at 03:14:13PM +0000, Lorenzo Pieralisi wrote: > > > According to the PCI local bus specifications (Revision 3.0, 3.2.5), > > > I/O Address space transactions are non-posted. On architectures where > > > I/O space is implemented through a chunk of memory mapped space mapped > > > to PCI address space (ie IA64/ARM/ARM64) the memory mapping for the > > > region backing I/O Address Space transactions determines the I/O > > > transactions attributes (before the transactions actually reaches the > > > PCI bus where it is handled according to the PCI specifications). > > > > > > Current pci_remap_iospace() interface, that is used to map the PCI I/O > > > Address Space into virtual address space, use pgprot_device() as memory > > > attribute for the virtual address mapping, that in some architectures > > > (ie ARM64) provides non-cacheable but write bufferable mappings (ie > > > posted writes), > > > Gee wiz, I am glad this is so well documented. > > > > > which clash with the non-posted write behaviour for I/O > > > Address Space mandated by the PCI specifications. > > > > > > Update the prot ioremap_page_range() parameter in pci_remap_iospace() > > > to pgprot_noncached to ensure that the virtual mapping backing > > > I/O Address Space guarantee non-posted write transactions issued > > > when addressing I/O Address Space through the MMIO mapping. > > How did we end up with pgprot_device() then in the first place Liviu Dudau [0] ? > I ask for two reasons: [replying using personal email as the corporate email system is taking its sweet time to deliver the email to my inbox] I've asked the people with the right knowledge about the correct API to use (Hi Catalin!), and during the review it did not throw any red flags. I guess, given Bjorn's comment, that everyone assumed AArch64 is the same as all other architectures and pgprot_device is synonymous to pgprot_noncached. > > a) should we then use a Fixes tag for this patch ? I'm not aware of issues being reported, but Lorenzo might have more info on this. > b) it does not seem clear what the semantics for pgprot_device() or even > pgprot_noncached(). Can you add some ? > > 8b921acfeffdb ("PCI: Add pci_remap_iospace() to map bus I/O resources") > > Also this patch claims archs can override this call alone, as its __weak. > So is the right thing to do to change pci_remap_iospace() to pgprot_noncached() > or is it for archs to add their own pci_remap_iospace()? If so why ? Without > proper semantics defined for these helpers this is all fuzzy. That was the initial intention, to let arches / platforms overwrite the whole pci_remap_iospace(). I guess the reality is that no one needs to overwrite it except for the AArch64 quirk, so probably easier to remove the __weak and fix the attributes for arm64. Best regards, Liviu > > > > Signed-off-by: Lorenzo Pieralisi > > > Cc: Arnd Bergmann > > > Cc: Will Deacon > > > Cc: Bjorn Helgaas > > > Cc: Russell King > > > Cc: Catalin Marinas > > > --- > > > drivers/pci/pci.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > > > index bd98674..bfb3c6e 100644 > > > --- a/drivers/pci/pci.c > > > +++ b/drivers/pci/pci.c > > > @@ -3375,7 +3375,7 @@ int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) > > > return -EINVAL; > > > > > > return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr, > > > - pgprot_device(PAGE_KERNEL)); > > > + pgprot_noncached(PAGE_KERNEL)); > > > > pgprot_device() is equivalent to pgprot_noncached() on all arches > > except ARM64, and I trust you're doing the right thing on ARM64, so > > I'm fine with this from a PCI perspective. > > > > I do find this puzzling because I naively expected pgprot_noncached() > > to match up with ioremap_nocache(), and apparently it doesn't. > > > > For example, ARM64 ioremap_nocache() uses PROT_DEVICE_nGnRE, which > > doesn't match the MT_DEVICE_nGnRnE in pgprot_noncached(). > > > > The point of these patches is to use non-posted mappings. Apparently > > you can do that with pgprot_noncached() here, but ioremap_nocache() > > isn't enough for the config space mappings? > > This is for iospace it seems, so the other patch I think was for > config space. > > Luis > > > I suppose that's a consequence of the pgprot_noncached() vs > > ioremap_nocache() mismatch, but this is all extremely confusing. > > > > > #else > > > /* this architecture does not have memory mapped I/O space, > > > so this function should never be called */ > > > -- > > > 2.10.0 > > > > > > > > > _______________________________________________ > > > linux-arm-kernel mailing list > > > linux-arm-kernel@lists.infradead.org > > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > > > > -- > Luis Rodriguez, SUSE LINUX GmbH > Maxfeldstrasse 5; D-90409 Nuernberg -- _ _|_|_ ('_') (⊃ )⊃ |_|_|