From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
To: Denys Vlasenko <dvlasenk@redhat.com>
Cc: brgerst@gmail.com, torvalds@linux-foundation.org,
akpm@linux-foundation.org, luto@amacapital.net,
linux-kernel@vger.kernel.org, jpoimboe@redhat.com,
luto@kernel.org, peterz@infradead.org, bp@alien8.de,
hpa@zytor.com, dave.hansen@intel.com, tglx@linutronix.de,
mingo@kernel.org, linux-tip-commits@vger.kernel.org
Subject: Re: [tip:x86/mm] x86/asm: Remove __VIRTUAL_MASK_SHIFT==47 assert
Date: Wed, 5 Apr 2017 15:00:30 +0300 [thread overview]
Message-ID: <20170405120029.ckl2a5bc3ikydozw@black.fi.intel.com> (raw)
In-Reply-To: <ccde7771-0bfc-579f-5682-ea7bb130205a@redhat.com>
On Wed, Apr 05, 2017 at 01:50:27PM +0200, Denys Vlasenko wrote:
> Er.... "Change top bits ... ((47 or 56 [bits] depending on paging mode)"?
> I know that's wrong and that's not what you meant to say,
> but it can be read this way too. "47th" instead of "47"
> would eliminate this reading, but you removed "th".
>
> Spell it out to eliminate any chance of confusion:
>
> Change top bits to match most significant bit (47th or 56th bit
> depending on paging mode) in the address.
>
---------------------8<-----------------------
>From 5dec28ba49387ff444e447213b553506e253616d Mon Sep 17 00:00:00 2001
From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Date: Wed, 5 Apr 2017 14:06:15 +0300
Subject: [PATCH] x86/asm: Fix comment in return_from_SYSCALL_64
On x86-64 __VIRTUAL_MASK_SHIFT depends on paging mode now.
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
---
arch/x86/entry/entry_64.S | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S
index 607d72c4a485..edec30584eb8 100644
--- a/arch/x86/entry/entry_64.S
+++ b/arch/x86/entry/entry_64.S
@@ -266,7 +266,8 @@ return_from_SYSCALL_64:
* If width of "canonical tail" ever becomes variable, this will need
* to be updated to remain correct on both old and new CPUs.
*
- * Change top 16 bits to be the sign-extension of 47th bit
+ * Change top bits to match most significant bit (47th or 56th bit
+ * depending on paging mode) in the address.
*/
shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
--
Kirill A. Shutemov
next prev parent reply other threads:[~2017-04-05 12:02 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-30 8:07 [PATCHv3 0/7] x86: 5-level paging enabling for v4.12, Part 3 Kirill A. Shutemov
2017-03-30 8:07 ` [PATCHv3 1/7] x86/boot: Detect 5-level paging support Kirill A. Shutemov
2017-04-04 8:28 ` [tip:x86/mm] " tip-bot for Kirill A. Shutemov
2017-03-30 8:07 ` [PATCHv3 2/7] x86/asm: Remove __VIRTUAL_MASK_SHIFT==47 assert Kirill A. Shutemov
2017-04-04 8:29 ` [tip:x86/mm] " tip-bot for Kirill A. Shutemov
2017-04-04 15:36 ` Denys Vlasenko
2017-04-05 11:12 ` Kirill A. Shutemov
2017-04-05 11:50 ` Denys Vlasenko
2017-04-05 12:00 ` Kirill A. Shutemov [this message]
2017-04-11 7:12 ` Ingo Molnar
2017-03-30 8:07 ` [PATCHv3 3/7] x86/mm: Define virtual memory map for 5-level paging Kirill A. Shutemov
2017-04-04 8:29 ` [tip:x86/mm] " tip-bot for Kirill A. Shutemov
2017-03-30 8:07 ` [PATCHv3 4/7] x86/paravirt: Make paravirt code support " Kirill A. Shutemov
2017-04-04 8:30 ` [tip:x86/mm] x86/paravirt: Add 5-level support to the paravirt code tip-bot for Kirill A. Shutemov
2017-03-30 8:07 ` [PATCHv3 5/7] x86/mm: Add basic defines/helpers for CONFIG_X86_5LEVEL Kirill A. Shutemov
2017-04-04 8:30 ` [tip:x86/mm] x86/mm: Add basic defines/helpers for CONFIG_X86_5LEVEL=y tip-bot for Kirill A. Shutemov
2017-03-30 8:07 ` [PATCHv3 6/7] x86/kasan: Extend to support 5-level paging Kirill A. Shutemov
2017-04-04 8:31 ` [tip:x86/mm] x86/kasan: Extend KASAN " tip-bot for Kirill A. Shutemov
2017-03-30 8:07 ` [PATCHv3 7/7] x86/espfix: Add " Kirill A. Shutemov
2017-04-04 8:31 ` [tip:x86/mm] x86/espfix: Add support for " tip-bot for Kirill A. Shutemov
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