From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755696AbdDFQST (ORCPT ); Thu, 6 Apr 2017 12:18:19 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:47126 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933468AbdDFQSH (ORCPT ); Thu, 6 Apr 2017 12:18:07 -0400 From: Alexandre Belloni To: Thomas Gleixner , Boris Brezillon Cc: Jason Cooper , Marc Zyngier , linux-kernel@vger.kernel.org, Alexandre Belloni Subject: [PATCH] irqchip/atmel-aic5: handle suspend to RAM Date: Thu, 6 Apr 2017 18:17:53 +0200 Message-Id: <20170406161753.4357-1-alexandre.belloni@free-electrons.com> X-Mailer: git-send-email 2.11.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On sama5d2, VDD core may be cut while suspending to RAM. This means the AIC5 registers content is lost. Restore it at resume time. Signed-off-by: Alexandre Belloni --- drivers/irqchip/irq-atmel-aic5.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c index 2a624d87a035..ddbf60251b0e 100644 --- a/drivers/irqchip/irq-atmel-aic5.c +++ b/drivers/irqchip/irq-atmel-aic5.c @@ -150,6 +150,8 @@ static int aic5_set_type(struct irq_data *d, unsigned type) } #ifdef CONFIG_PM +u32 smr_cache[128]; + static void aic5_suspend(struct irq_data *d) { struct irq_domain *domain = d->domain; @@ -159,6 +161,11 @@ static void aic5_suspend(struct irq_data *d) int i; u32 mask; + for (i = 0; i < domain->revmap_size; i++) { + irq_reg_writel(bgc, i, AT91_AIC5_SSR); + smr_cache[i] = irq_reg_readl(bgc, AT91_AIC5_SMR); + } + irq_gc_lock(bgc); for (i = 0; i < dgc->irqs_per_chip; i++) { mask = 1 << i; @@ -184,10 +191,16 @@ static void aic5_resume(struct irq_data *d) u32 mask; irq_gc_lock(bgc); + + irq_reg_writel(bgc, 0xffffffff, AT91_AIC5_SPU); + for (i = 0; i < domain->revmap_size; i++) { + irq_reg_writel(bgc, i, AT91_AIC5_SSR); + irq_reg_writel(bgc, i, AT91_AIC5_SVR); + irq_reg_writel(bgc, smr_cache[i], AT91_AIC5_SMR); + } + for (i = 0; i < dgc->irqs_per_chip; i++) { mask = 1 << i; - if ((mask & gc->mask_cache) == (mask & gc->wake_active)) - continue; irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR); if (mask & gc->mask_cache) -- 2.11.0