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Date: Sun, 9 Apr 2017 13:13:33 +0100
From: Marc Zyngier <marc.zyngier@arm.com>
To: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
        Boris Brezillon <boris.brezillon@free-electrons.com>,
        Jason Cooper <jason@lakedaemon.net>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] irqchip/atmel-aic5: handle suspend to RAM
Message-ID: <20170409131333.76a7e7a1@why.wild-wind.fr.eu.org>
In-Reply-To: <20170406161753.4357-1-alexandre.belloni@free-electrons.com>
References: <20170406161753.4357-1-alexandre.belloni@free-electrons.com>
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On Thu, 6 Apr 2017 18:17:53 +0200
Alexandre Belloni <alexandre.belloni@free-electrons.com> wrote:

> On sama5d2, VDD core may be cut while suspending to RAM. This means the
> AIC5 registers content is lost. Restore it at resume time.
> 
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
>  drivers/irqchip/irq-atmel-aic5.c | 17 +++++++++++++++--
>  1 file changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c
> index 2a624d87a035..ddbf60251b0e 100644
> --- a/drivers/irqchip/irq-atmel-aic5.c
> +++ b/drivers/irqchip/irq-atmel-aic5.c
> @@ -150,6 +150,8 @@ static int aic5_set_type(struct irq_data *d, unsigned type)
>  }
>  
>  #ifdef CONFIG_PM
> +u32 smr_cache[128];

Two things:

- Why isn't this array static?
- Why is the size hard-coded to 128, while the loops below are based on
  the domain revmap_size.

> +
>  static void aic5_suspend(struct irq_data *d)
>  {
>  	struct irq_domain *domain = d->domain;
> @@ -159,6 +161,11 @@ static void aic5_suspend(struct irq_data *d)
>  	int i;
>  	u32 mask;
>  
> +	for (i = 0; i < domain->revmap_size; i++) {
> +		irq_reg_writel(bgc, i, AT91_AIC5_SSR);
> +		smr_cache[i] = irq_reg_readl(bgc, AT91_AIC5_SMR);
> +	}
> +

This seem to affect more than just the sama5d2 part. Is that expected?

>  	irq_gc_lock(bgc);
>  	for (i = 0; i < dgc->irqs_per_chip; i++) {
>  		mask = 1 << i;
> @@ -184,10 +191,16 @@ static void aic5_resume(struct irq_data *d)
>  	u32 mask;
>  
>  	irq_gc_lock(bgc);
> +
> +	irq_reg_writel(bgc, 0xffffffff, AT91_AIC5_SPU);
> +	for (i = 0; i < domain->revmap_size; i++) {
> +		irq_reg_writel(bgc, i, AT91_AIC5_SSR);
> +		irq_reg_writel(bgc, i, AT91_AIC5_SVR);
> +		irq_reg_writel(bgc, smr_cache[i], AT91_AIC5_SMR);
> +	}
> +
>  	for (i = 0; i < dgc->irqs_per_chip; i++) {
>  		mask = 1 << i;
> -		if ((mask & gc->mask_cache) == (mask & gc->wake_active))
> -			continue;
>  
>  		irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);
>  		if (mask & gc->mask_cache)


Thanks,

	M.
-- 
Without deviation from the norm, progress is not possible.