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Date: Mon, 10 Apr 2017 12:34:05 +0200
From: Borislav Petkov <bp@alien8.de>
To: Piotr Luc <piotr.luc@intel.com>
Cc: linux-edac@vger.kernel.org, Tony Luck <tony.luck@intel.com>,
        Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>,
        "H. Peter Anvin" <hpa@zytor.com>, x86@kernel.org,
        linux-kernel@vger.kernel.org,
        Dave Hansen <dave.hansen@linux.intel.com>
Subject: Re: [PATCH v1] x86/mce: enable PPIN for Knights Landing/Mill
Message-ID: <20170410103405.q7xfjf5ohnzroz2l@pd.tnic>
References: <20170408172004.8463-1-piotr.luc@intel.com>
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On Sat, Apr 08, 2017 at 07:20:04PM +0200, Piotr Luc wrote:
> Intel Xeon Phi processors (KNL and KNM) do support PPIN as well, so we
> add their CPUIDs to the whitelist of supported processors.
> PPIN is a unique number that allows to determine origin of the CPU,
> from now on will be logged when an mce error occur.
> 
> Signed-off-by: Piotr Luc <piotr.luc@intel.com>
> ---
>  arch/x86/kernel/cpu/mcheck/mce_intel.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
> index 190b3e6..f1c44c3 100644
> --- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
> +++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
> @@ -481,6 +481,8 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
>  	case INTEL_FAM6_BROADWELL_XEON_D:
>  	case INTEL_FAM6_BROADWELL_X:
>  	case INTEL_FAM6_SKYLAKE_X:
> +	case INTEL_FAM6_XEON_PHI_KNL:
> +	case INTEL_FAM6_XEON_PHI_KNM:
>  		if (rdmsrl_safe(MSR_PPIN_CTL, &val))
>  			return;
>  
> -- 

Applied, thanks.

-- 
Regards/Gruss,
    Boris.

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